[SAM9G20] We have some problem in using SDRAM.

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byuljigi
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Joined: Fri Feb 24, 2017 12:53 pm

[SAM9G20] We have some problem in using SDRAM.

Fri Feb 24, 2017 1:04 pm

Dear Sir

This is yoo from Shina System Korea and we are using ISSI SDRAM.
and we have some problem in using your ISSI SDRAM.

Environment:
CPU : ATMEL AT91SAM9G20(doc6384).pdf
SDRAM : ISSI_42-45S83200G-16160G-258274.pdf

Our System : (shared memory bus)
CPU |<---------------------> SDRAM
|<---------------------> NAND
|<---------------------> SRAM
|<---------------------> LCD

Status:
Our system go to hangup without time period.
It goes one month OK , but sometime, it goes to hangup within one day.
Our system has power noise inself because it use many types of power ( 24V AV, 24VDC , 12VDC, 5VDC, 3.3VDC, 1.8VDC )

Issue:
AT91SAM9G20 CPU does memory control with ChipSel Low always.
So we are checking with ATMEL FAE. We do not know it is normal operation.
In ChipData sheet, Chipsel signal is active low and the signal is pull-up on our board.

Question:
Can "ISSI SDRAM" work normal with ChipSel Low ?
( Our CPU keep Chipsel Low from bootloader..... )

Chipsel definition in DATASHEET:
1. ISSI : " CS Input The CS input determines whether command input is enabled within the device.
Command input is enabled when CS is LOW, and disabled with CS is HIGH. The
device remains in the previous state when CS is HIGH.
2.CPU :


Addition information:
- CPU work : 400M
- Memory work : 133M
16Bit Bus I/F

- SDRAM initial code in CPU:
void BOARD_ConfigureSdram(unsigned char busWidth)
{
volatile unsigned int i;
static const Pin pinsSdram = PINS_SDRAM;
volatile unsigned int *pSdram = (unsigned int *) AT91C_EBI_SDRAM;
unsigned short sdrc_dbw = 0;
unsigned int tmp = 0;


switch (busWidth) {
case 16:
sdrc_dbw = AT91C_SDRAMC_DBW_16_BITS;
break;
case 32:
default:

sdrc_dbw = AT91C_SDRAMC_DBW_32_BITS;
/* Just need for busWidth 32bit, PINS_SDRAM's mask is about D16~D31 */
PIO_Configure(&pinsSdram, 1);
break;
}

// Enable EBI chip select for the SDRAM
tmp = READ(AT91C_BASE_MATRIX, MATRIX_EBI) | AT91C_MATRIX_CS1A_SDRAMC;
WRITE(AT91C_BASE_MATRIX, MATRIX_EBI, tmp);

WRITE(AT91C_BASE_SDRAMC, SDRAMC_CR, AT91C_SDRAMC_NC_9
| AT91C_SDRAMC_NR_13
| AT91C_SDRAMC_CAS_2 // Clock Cycle = 7.5ns<
| AT91C_SDRAMC_NB_4_BANKS
| sdrc_dbw
| AT91C_SDRAMC_TWR_2 // tDPL 14ns< 7.5 X 2 = 15ns
| AT91C_SDRAMC_TRC_8 // 60ns< 7.5 X 8 = 60ns
| AT91C_SDRAMC_TRP_2 // 15ns< 7.5 X 2 = 15ns
| AT91C_SDRAMC_TRCD_2 // 15ns< 7.5 X 2 = 15ns
| AT91C_SDRAMC_TRAS_5 // 37ns< <100k 7.5 X 5 = 37.5ns
| AT91C_SDRAMC_TXSR_10);// 70ns< 7.5 X 10 = 75ns

for (i = 0; i < 1000; i++);
WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_NOP_CMD); // Perform NOP
pSdram[0] = 0x00000000;

WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_PRCGALL_CMD); // Set PRCHG AL
pSdram[0] = 0x00000000; // Perform PRCHG

for (i = 0; i < 10000; i++);

WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD); // Set 1st CBR
pSdram[1] = 0x00000001; // Perform CBR

WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD); // Set 2 CBR
pSdram[2] = 0x00000002; // Perform CBR

WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD); // Set 3 CBR
pSdram[3] = 0x00000003; // Perform CBR

WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD); // Set 4 CBR
pSdram[4] = 0x00000004; // Perform CBR

WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD); // Set 5 CBR
pSdram[5] = 0x00000005; // Perform CBR

WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD); // Set 6 CBR
pSdram[6] = 0x00000006; // Perform CBR

WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD); // Set 7 CBR
pSdram[7] = 0x00000007; // Perform CBR

WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD); // Set 8 CBR
pSdram[8] = 0x00000008; // Perform CBR

WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_LMR_CMD); // Set LMR operation
pSdram[9] = 0xcafedede; // Perform LMR burst=1, lat=2

WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_NORMAL_CMD); // Set Normal mode
pSdram[0] = 0x00000000; // Perform Normal mode

WRITE(AT91C_BASE_SDRAMC, SDRAMC_TR, (BOARD_MCK * 7) / 1000000); // Set Refresh Timer
for (i = 0; i < 10000; i++);
}

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