SDRAM timing requirements

Discussion around AT91RM9200 and SAM9 Series Products.

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SDRAM timing requirements

Fri Feb 10, 2017 10:35 am

I am interfacing a Micron MT48H16M32LFCM-75 SDRAM with an Atmel AT91SAM9G20 and I need to verify on paper (as far as possible), that the timing specifications between those two devices are compatible.

However, I have trouble matching some parameters from the Atmel data sheet against the parameters from the Micron SDRAM.

AT91SAM9G20 SDRAM timings:
Image
MT48H16M32LFCM-75 timings:
Image
I manage to compare CKE, CS, CAS, RAS, DQM, BA, WE and Address setup and hold times (2.0ns and 1.0ns respectively) between the two tables.

What I am unsure about is:

What is Data Out Access time (Atmel specs) referring to?
What is Data Out change time (Atmel specs) referring to?
I don't find any information in the Atmel data sheet regarding the 100/133MHz clock stability / timing to check against the clock requirements of the SDRAM.

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