SAMA5D4 XULT board IAR examples fail to load

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jmore
Posts: 1
Joined: Fri Jun 23, 2006 8:57 pm

SAMA5D4 XULT board IAR examples fail to load

Wed Oct 05, 2016 11:47 pm

Hi,

I am evaluating the SAMA5D4 using the Explained board and the latest IAR IDE. I downloaded the sama5d4x-xult software pack. However when I try and download and debug the getting started example either with a Segger J-Link or the EDBG/Segger (I reflashed the EDBG chip) I get memory errors like this (Debug Log from IAR):

Wed Oct 05, 2016 14:42:58: IAR Embedded Workbench 7.70.2 (armproc.dll)
Wed Oct 05, 2016 14:42:58: Loaded macro file: C:\Program Files (x86)\IAR Systems\Embedded Workbench 7.5\arm\config\debugger\Atmel\SAMA5D4.dmac
Wed Oct 05, 2016 14:42:58: Loaded macro file: O:\aProjects\SLCD-SAMA5\IAR\sama5d4x-xult\examples\getting-started\build\ewarm\..\..\..\..\libraries\libboard_sama5d4x\resources\ewarm\sama5d4x-xult-sram.mac
Wed Oct 05, 2016 14:42:58: JLINK command: ProjectFile = O:\aProjects\SLCD-SAMA5\IAR\sama5d4x-xult\examples\getting-started\build\ewarm\settings\getting-started_sram.jlink, return = 0
Wed Oct 05, 2016 14:42:58: Device "ATSAMA5D44" selected.
Wed Oct 05, 2016 14:42:58: DLL version: V6.0h, compiled Sep 1 2016 19:00:33
Wed Oct 05, 2016 14:42:58: Firmware: J-Link EDBG compiled May 3 2016 15:18:23
Wed Oct 05, 2016 14:42:58: JTAG speed is initially set to: 32 kHz
Wed Oct 05, 2016 14:42:58: Initial reset was performed
Wed Oct 05, 2016 14:42:58: TotalIRLen = 4, IRPrint = 0x01
Wed Oct 05, 2016 14:42:58: ARM AP[0]: 0x24770002, APB-AP
Wed Oct 05, 2016 14:42:58: ROMTbl 0 [0]: 00010003, CID: B105900D, PID:04-001BBC05 Cortex-A5
Wed Oct 05, 2016 14:42:58: Found Cortex-A5 r0p1
Wed Oct 05, 2016 14:42:58: 3 code breakpoints, 2 data breakpoints
Wed Oct 05, 2016 14:42:58: Debug architecture ARMv7.0
Wed Oct 05, 2016 14:42:58: Data endian: little
Wed Oct 05, 2016 14:42:58: Main ID register: 0xC10FC051
Wed Oct 05, 2016 14:42:58: I-Cache L1: 32 KB, 512 Sets, 32 Bytes/Line, 2-Way
Wed Oct 05, 2016 14:42:58: D-Cache L1: 32 KB, 256 Sets, 32 Bytes/Line, 4-Way
Wed Oct 05, 2016 14:42:58: System control register:
Wed Oct 05, 2016 14:42:58: Instruction endian: little
Wed Oct 05, 2016 14:42:58: Level-1 instruction cache enabled
Wed Oct 05, 2016 14:42:58: Level-1 data cache disabled
Wed Oct 05, 2016 14:42:58: MMU disabled
Wed Oct 05, 2016 14:42:58: Branch prediction enabled
Wed Oct 05, 2016 14:42:58: Found 1 JTAG device, Total IRLen = 4:
Wed Oct 05, 2016 14:42:58: #0 Id: 0x4BA00477, IRLen: 4, IRPrint: 0x1 CoreSight JTAG-DP
Wed Oct 05, 2016 14:42:58: ------------------------------ execUserPreload ---------------------------------
Wed Oct 05, 2016 14:42:58: ------------------------ Watchdog Disable ------------------------
Wed Oct 05, 2016 14:42:58: ---------------------------------------- Chip ID 0x0A5C07C0
Wed Oct 05, 2016 14:43:00: 13892 bytes downloaded and verified (7.91 Kbytes/sec)
Wed Oct 05, 2016 14:43:00: Warning:
Verify error at address 0x00200000, target byte: 0xE5, byte in file: 0x88
Wed Oct 05, 2016 14:43:00: Warning:
Verify error at address 0x00200001, target byte: 0x9F, byte in file: 0xF0

Since these examples are for the board I'm using I am not sure what is going wrong. None of the examples seen to be able to be downloaded and debugged.

Thanks
blue_z
Location: USA
Posts: 1498
Joined: Thu Apr 19, 2007 10:15 pm

Re: SAMA5D4 XULT board IAR examples fail to load

Fri Oct 07, 2016 1:47 am

Does your SBC work normally, i.e. you can boot the pre-installed Linux demo?

You joined this site before I did.
Does that mean you're experienced with IAR and/or Atmel ARM SoCs?
jmore wrote:IWed Oct 05, 2016 14:43:00: 13892 bytes downloaded and verified (7.91 Kbytes/sec)
The "binary" file that you downloaded to the target is only 13892 bytes.
The pre-built sram.bin file in the package is 14904 bytes.
The log you posted doesn't indicate what you did. What file did you download to the target?
jmore wrote:Wed Oct 05, 2016 14:43:00: Warning:
Verify error at address 0x00200000, target byte: 0xE5, byte in file: 0x88
Wed Oct 05, 2016 14:43:00: Warning:
Verify error at address 0x00200001, target byte: 0x9F, byte in file: 0xF0
This looks like an endian issue.
The first four bytes of sram.bin are 88 F0 9F E5, which should form the vector instruction word 0xE59FF088 at 0x200000.
The target seems to have the instruction word stored in big-endian order.

Regards

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