DDR Power comsumption on SAMA5D3CM

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bobmorane
Posts: 8
Joined: Fri Apr 02, 2010 9:55 am

DDR Power comsumption on SAMA5D3CM

Thu Aug 01, 2013 5:46 pm

Hi all,
We're using a SAMA5D35cm (from Ronetix) with Atmel SAMA5D35ek running Linux. So far, so good.

We've then designed a minimal prototype mother board to evaluate power consumption of the module (3.3V + Uart Debug + boot logic, that's it, nothing else). The board boot fine with Linux kernel 3.6.9 (with DT and ubi FS).

Our problem is power consumption.
With our MB :
At prompt we have 514mW
When going in slow clock we have 346mW

Slow clock number is really high.
I evaluated that we should be bellow 100mW (Ethernet chip in low conso + DDR in self refresh + CPU in slowclock + Flash and other chips)

It seems to me that the DDR do not go in self refresh state.
I've tryed to remove the DDR self reflesh call in pm.h and pm_slowclock.S and I can't see any real change in consumption.

Are we sure that the PM code for DDR with SAMA5D5x in Linux is OK ?
Anyone have experience with that ?

Thanks all for any answer,
BR,
V.
bobmorane
Posts: 8
Joined: Fri Apr 02, 2010 9:55 am

Re: DDR Power comsumption on SAMA5D3CM

Mon Aug 05, 2013 11:24 am

The Giga Ethernet PHY was not entering in suspend because the following was missing in sama5d3mb.dtsi :

macb0: ethernet@f0028000 {
phy-mode = "rgmii";
};

Now the PHY goes in suspend mode.
I've also disabled the RED led (more than 25mW !!!!!).

Now in slow clock I get : 162mW.

This is still too high ... My target is under 100mW

V.
bobmorane
Posts: 8
Joined: Fri Apr 02, 2010 9:55 am

Re: DDR Power comsumption on SAMA5D3CM

Tue Sep 10, 2013 3:18 pm

Hi all,

As I'am not a RAM expert, I'am trying to figure out how the DDR2RAM is configurated and initialized and why the self refresh seems not to be activated when going to slow clock.

In the Atmel SAMA5D53 main doc I can read page 309 :
"Self refresh mode is used in power-down mode, i.e., when no access to the DDR-SDRAM device is possible."

I'am puzzled with this sentence : What does it mean ? Should we configure the DDR in power-down mode first before going to SR ? The state machine diagram in Micron documentation do not show that.
The self refresh is entered when SR command is sent by the MPDDRC and then CKE goes to low and CK/CK# are 0V.

Unfortunatly I can't prob CKE/CK/CK# as they are routed only on the module (no external pin or test point).

I've check ether the DDR2RAM init in bootstrap code and pm_clowclock.S, but all seems OK to me.

Any help would be very appreciated.
Thanks,
V.

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