can the SDRAM sdck be lowered?

Discussions around product based on ARM Cortex M7 core.
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koch
Posts: 4
Joined: Tue Sep 16, 2014 1:57 am

can the SDRAM sdck be lowered?

Thu Oct 01, 2015 2:16 am

or is it tied to the bus matrix (150 Mhz) meaning I have to lower the whole processor's frequency?

I ask because in the SAM V71 Xplained Ultra user guide it says:

"Plugging a cable into the LCD connector creates routing stubs for the on-board SDRAM which
creates ringing. The ringing will reduce the maximum SDRAM communication frequency."

So the question is how do I accomplish such reduction? In the stm32f7 manual it clearly states a method for 1/3 or 2/3 reduction but I cannot find something similar on Atmel's chip!
koch
Posts: 4
Joined: Tue Sep 16, 2014 1:57 am

Re: can the SDRAM sdck be lowered?

Thu Oct 01, 2015 2:15 pm

ok I found the answer, I guess SDCK=MCK which can be divided from HCLK (not an option on the ATSAM3S I am working with now) so I do not need to lower processor speed down to 75 Mhz SDCK. Only problem is GPIO communication rate will suffer, in contrast to stm32f7 where SDRAM speed is completely separate.

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