or is it tied to the bus matrix (150 Mhz) meaning I have to lower the whole processor's frequency?
I ask because in the SAM V71 Xplained Ultra user guide it says:
"Plugging a cable into the LCD connector creates routing stubs for the on-board SDRAM which
creates ringing. The ringing will reduce the maximum SDRAM communication frequency."
So the question is how do I accomplish such reduction? In the stm32f7 manual it clearly states a method for 1/3 or 2/3 reduction but I cannot find something similar on Atmel's chip!
Discussions around product based on ARM Cortex M7 core.
2 posts • Page 1 of 1
ok I found the answer, I guess SDCK=MCK which can be divided from HCLK (not an option on the ATSAM3S I am working with now) so I do not need to lower processor speed down to 75 Mhz SDCK. Only problem is GPIO communication rate will suffer, in contrast to stm32f7 where SDRAM speed is completely separate.
Who is online
Users browsing this forum: No registered users and 4 guests