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SAMA5D27-SOM1 LCDC Sync - Bare metal

Posted: Thu May 17, 2018 4:48 pm
by iguffick
I'm using the SAMA5D27-SOM1 with the SoftPack bare-metal C library from:
https://github.com/atmelcorp/atmel-software-package

Using the LCDC example I can get a working display with overlays bouncing around the screen, debug in IAR etc. All fine.

Using this example as a starting point, I've modified it to keep one of the overlay windows at a fixed position and scroll it's contents up a line at a time.
This shows up screen tearing effects as the buffer update is not synchronised to the blanking of the display.

Q1. Is there a way of synchronising screen updates so that they happen during the blanking period?

Q2. I am scrolling using a simple memcpy from line 2 to line 1 for the size of the overlay buffer.
I had also tried scrolling by having a double size buffer and changing the buffer start from line1, line 2, line 3 etc.
But this corrupted the overlay contents whilst writing to the registers, which cleared and showed the initial contents when I did a 'break'.
Is there any reason why changing the buffer start would corrupt in this way?

Thanks for any help or insight offered.
Regards,
Ian.

Re: SAMA5D27-SOM1 LCDC Sync - Bare metal

Posted: Fri May 18, 2018 12:19 am
by blue_z
iguffick wrote:But this corrupted the overlay contents whilst writing to the registers, which cleared and showed the initial contents when I did a 'break'.
Is there any reason why changing the buffer start would corrupt in this way?
I'm not familiar with the LCDC, and your ambiguous reference to "registers" conveys no information as to what you're doing.
The datasheet mentions several "frame buffer base address" registers, but other than defines in various component_lcdc.h header files, there seems to be no usage of those registers in the Softpack.
I would have thought that "changing the buffer start" would involve modifying a DMA descriptor (in memory) rather than a register.

DMA buffer chaining and manipulation of linked lists could also be used to achieve scrolling.

Regards

Re: SAMA5D27-SOM1 LCDC Sync - Bare metal

Posted: Fri May 18, 2018 2:06 pm
by iguffick
Ok, I wasn't looking at the way the DMAs are used. In the function "lcdc_put_image_rotated()" in drivers/dipslay/lcdc.c the buffer is assigned to the addr of the DMA decsriptor.
data->dma_desc->addr = (uint32_t)buffer;

Can this be updated whilst the DMA is active, i.e. update and the new value would be used the next time the DMA starts. Or does the DMA need to be disabled, modify the value then restart (which couldn't be done whilst the DMA is active without screen corruption).

Back to my Q1.
Is the 'End of DMA Transfer' interrupt effectively the start of the vertical blanking?
But then there are separate 'End of DMA transfer' for the base, overlay1,overlay2, and heo. How do they differ?

Ian.