Missing info on some SAMA5D27-SIP pins

Discussion around products based on ARM Cortex-A5 core.

Moderator: nferre

bmpenrod
Posts: 16
Joined: Wed Feb 07, 2018 9:39 pm

Missing info on some SAMA5D27-SIP pins

Wed Feb 14, 2018 2:58 am

I'm designing a custom board using the SAMA5D27-SIP, which has internal DDR2. I am using the SAMA5D27-SOM1-EK as a reference design. I've run into a few signals that are either completely undocumented, or partially documented using all of the docs I am aware of.

First the completely undocumented:

ODT, on pin D17. I know this is typically handled by the DDR2 controllor. Since the DDR2 is internal to this chip, I don't know what is supposed to be done with this pin.

DDR_VREF, on pins J10 and F11. This is normally created by resistively splitting the DDR2 supply voltage and bypassing it with caps. There is no guidance as to what to do with this pin in the SAMA5D27-SIP datasheet, or an example shown in the SAMA5D27-SOM1 docs. I could guess what to do here, but I'd rather not.

Seems like the complete schematic of the SOM would be a good thing for MicroChip to release as a reference design for the SIP.

Now the incompletely documented from the SAMA5D2 and SAMA5D27-SIP datasheets:

PIOBUF0-7, RXD, COMPP, COMPN, related to the tamper pins, are mentioned in the docs, but there is no info on the input circuit residing in the chip, i.e. floating, pulled up, pulled down, etc. The SAMA5D27-SOM1-EK docs seems to show that these are being left floating. An unstuffed connector is present on the board to do something with them if desired. Normally I would expect some discussion in the datasheet about what to do if these are not used...but alas I cannot find such discussion.
thackerp
Posts: 6
Joined: Tue Jul 19, 2016 10:19 pm

Re: Missing info on some SAMA5D27-SIP pins

Mon Feb 19, 2018 5:26 pm

bmpenrod wrote:
Wed Feb 14, 2018 2:58 am
I'm designing a custom board using the SAMA5D27-SIP, which has internal DDR2. I am using the SAMA5D27-SOM1-EK as a reference design. I've run into a few signals that are either completely undocumented, or partially documented using all of the docs I am aware of.

First the completely undocumented:

ODT, on pin D17. I know this is typically handled by the DDR2 controllor. Since the DDR2 is internal to this chip, I don't know what is supposed to be done with this pin.

DDR_VREF, on pins J10 and F11. This is normally created by resistively splitting the DDR2 supply voltage and bypassing it with caps. There is no guidance as to what to do with this pin in the SAMA5D27-SIP datasheet, or an example shown in the SAMA5D27-SOM1 docs. I could guess what to do here, but I'd rather not.

Seems like the complete schematic of the SOM would be a good thing for MicroChip to release as a reference design for the SIP.

The ODT pin should be grounded. Your instinct on DDR_VREF is correct. The SOM schematic, datasheet and other docs should go live on the website today or tomorrow.


Now the incompletely documented from the SAMA5D2 and SAMA5D27-SIP datasheets:

PIOBUF0-7, RXD, COMPP, COMPN, related to the tamper pins, are mentioned in the docs, but there is no info on the input circuit residing in the chip, i.e. floating, pulled up, pulled down, etc. The SAMA5D27-SOM1-EK docs seems to show that these are being left floating. An unstuffed connector is present on the board to do something with them if desired. Normally I would expect some discussion in the datasheet about what to do if these are not used...but alas I cannot find such discussion.

For information on the tamper pins, you need app note AN_44095. It's only available under NDA. To request it, you need to submit a support ticket.

Return to “SAMA5D Cortex-A5 MPU”

Who is online

Users browsing this forum: No registered users and 0 guests