GMAC_TISUBN availablity ?

For SAMA5D2 Xplained, SAMA5D3 Xplained and SAMA5D4 Xplained

Moderator: nferre

Posts: 3
Joined: Thu Jul 21, 2016 4:30 pm

GMAC_TISUBN availablity ?

Mon Jul 25, 2016 3:02 pm


I would like please to move, and update this discussion, to the right category and hopefully get a broader audience.
The topic is PTP/TSU support on the SAMA5d3

I received my new SAMA5d36 today, and I confirm that despite of what the documentation says,
( ... asheet.pdf, page 996) the GMAC_TISUBN register (0x1BC) does -not- seem to have any effect.

Moreover, reading the written value always reports "0x0".

Is this a documentation bug ? It this something expected on a more recent chip revision ?
If yes, from what version is it available, and where should I check the revision number ?
(parts list, chip register ...) ?

Implementing TSU clock adjustement with the "alternate" registers is really a pain in the neck,
I have some serious doubts on the precision of that method, considering the huge jitter I get.

What makes me think about a documentation bug, is also the fact that both methods
(alternate and subns) coexist, without saying that the former is likely deprecated or still
present on compatibility purpose.

Any help would be greatly appreciated

Return to “SAMA5 Xplained”

Who is online

Users browsing this forum: Baidu [Spider] and 2 guests