How to initialize ddram from scratch ?

Moderator: nferre

manes6969
Location: belgium
Posts: 16
Joined: Wed May 24, 2006 9:38 pm

How to initialize ddram from scratch ?

Thu Dec 11, 2014 1:16 pm

Hi

I'm trying to initialize the ddram from bare metal.
So far all went well , but problems when trying to init the sdram. Is there any source somewere ? I've managed to have it running , but only when I first connect to samba , and then reset the board. From power on running doesn't work. Here's my code in assembler :

;init the DDR2-SDRAM

ldr r0,=PMC_SCER ;enable ddr clock
mov r1,#0x04
str r1,[r0]
ldr r0,=PMC_PCER1 ;pid 49 on
mov r1,#0x00020000
str r1,[r0]
ldr r0,=MPDDRC_HS
ldr r1,[r0]
orr r1,r1,#0x00000020
str r1,[r0]
ldr r0,=MPDDRC_LPR
mov r1,#0x00000000
str r1,[r0]


ldr r0,=MPDDRC_DLL_SOF ;
ldr r1,=0x01010001
str r1,[r0]
ldr r0,=MPDDRC_DLL_MO ;
ldr r1,=0xc5011f07
str r1,[r0]
ldr r0,=MPDDRC_IO_CALIBR ;
ldr r1,=0x00000404
str r1,[r0]


ldr r0,=SFR_DDRCFG
ldr r1,=0x00030000
str r1,[r0]
ldr r0,=SFR_EBICFG
ldr r1,=0x0001030f
str r1,[r0]



;STEP1 - SET DEVICE TYPE
ldr r0,=MPDDRC_MD ;set ddr2-sdram - 32bit
mov r1,#0x00000006
str r1,[r0]
ldr r0,=MPDDRC_CR ;
ldr r1,=0x00f2003d
str r1,[r0]

;STEP2 - SET TIMING REGISTERS
ldr r0,=MPDDRC_TPR0 ;
ldr r1,=0x22228226
str r1,[r0]
ldr r0,=MPDDRC_TPR1 ;
ldr r1,=0x02c81c1a
str r1,[r0]
ldr r0,=MPDDRC_TPR2 ;
ldr r1,=0x00072278
str r1,[r0]

;STEP3 - ISSUE NOP COMMAND
ldr r0,=MPDDRC_MR ;
mov r1,#0x00000001
str r1,[r0]
ldr r0,=SDRAM_START ;
mov r1,#0x00000000
str r1,[r0]
;delay
mov r0,#0x8000
BL delay

;STEP4 - ISSUE NOP COMMAND
ldr r0,=MPDDRC_MR ;
mov r1,#0x00000001
str r1,[r0]
ldr r0,=SDRAM_START ;
mov r1,#0x00000000
str r1,[r0]
;delay
mov r0,#0x200
BL delay

;STEP5 - ISSUE ALL BANKS PRECHARGE
ldr r0,=MPDDRC_MR ;
mov r1,#0x00000002
str r1,[r0]
ldr r0,=SDRAM_START ;
mov r1,#0x00000000
str r1,[r0]
;delay
mov r0,#0x200
BL delay

;STEP6 - SET EMR OPERATION (EMRS2)
ldr r0,=MPDDRC_MR ;
mov r1,#0x00000005
str r1,[r0]
ldr r0,=(SDRAM_START+0X04000000) ;
mov r1,#0x00000000
str r1,[r0]
;delay
mov r0,#0x200
BL delay

;STEP7 - SET EMR OPERATION (EMRS3)
ldr r0,=MPDDRC_MR ;
mov r1,#0x00000005
str r1,[r0]
ldr r0,=(SDRAM_START+0X06000000) ;
mov r1,#0x00000000
str r1,[r0]
;delay
mov r0,#0x200
BL delay

;STEP8 - SET EMR OPERATION (EMRS1)
ldr r0,=MPDDRC_MR ;
mov r1,#0x00000005
str r1,[r0]
ldr r0,=(SDRAM_START+0X02000000) ;
mov r1,#0x00000000
str r1,[r0]
;delay
mov r0,#0x200
BL delay

;STEP9 - ENABLE DLL RESET
ldr r0,=MPDDRC_CR
ldr r1,[r0]
orr r1,r1,#0x00000080
str r1,[r0]

;STEP10 - RESET DLL
ldr r0,=MPDDRC_MR ;
mov r1,#0x00000003
str r1,[r0]
ldr r0,=(SDRAM_START) ;
mov r1,#0x00000000
str r1,[r0]
;delay
mov r0,#0x200
BL delay

;STEP11 - ISSUE ALL BANKS PRECHARGE
ldr r0,=MPDDRC_MR ;
mov r1,#0x00000002
str r1,[r0]
ldr r0,=SDRAM_START ;
mov r1,#0x00000000
str r1,[r0]
;delay
mov r0,#0x200
BL delay

;STEP12 - TWO AUTO REFRESH (CBR) CYCLES ARE PROVIDED.
; PROGRAM THE AUTO REFRESH COMMAND
ldr r0,=MPDDRC_MR ;
mov r1,#0x00000004
str r1,[r0]
ldr r0,=SDRAM_START ;
mov r1,#0x00000000
str r1,[r0]
;delay
mov r0,#0x200
BL delay

ldr r0,=MPDDRC_MR ;Set second CBR
mov r1,#0x00000004
str r1,[r0]
ldr r0,=SDRAM_START ;
mov r1,#0x00000000
str r1,[r0]
;delay
mov r0,#0x200
BL delay

;STEP13 - PROGRAM DLL FIELD TO LOW (DISABLE DLL RESET)
ldr r0,=MPDDRC_CR
ldr r1,[r0]
ldr r2,=0xffffff7f
and r1,r1,r2
str r1,[r0]

;STEP14 - A MODE SET (MRS) IS ISSUED TO PROGRAM THE PARAMETERS OF THE SDRAM
ldr r0,=MPDDRC_MR ;Set second CBR
mov r1,#0x00000003
str r1,[r0]
ldr r0,=SDRAM_START ;
mov r1,#0x00000000
str r1,[r0]
;delay
mov r0,#0x200
BL delay

;STEP15 - PROGRAM OCD FIELD INTO THE CONFIGURATION REGISTER TO HIGH
; (OCD CALIBRATION DEFAULT)
ldr r0,=MPDDRC_CR
ldr r1,[r0]
orr r1,r1,#0x00007000
str r1,[r0]

;STEP16 - AN EXTENDED MODE REGISTER SET (EMRS1) CYCLE IS ISSUED TO
; OCD DEFAULT VALUE
ldr r0,=MPDDRC_MR ;Set second CBR
mov r1,#0x00000005
str r1,[r0]
ldr r0,=(SDRAM_START+0x02000000) ;
mov r1,#0x00000000
str r1,[r0]
;delay
mov r0,#0x200
BL delay

;STEP17 - PROGRAM OCD FIELD IN THE CONFIGURATION REGISTER TO LOW
; (OCD CALIBRATION MODE EXIT)
ldr r0,=MPDDRC_CR
ldr r1,[r0]
ldr r2,=0xffff8fff
and r1,r1,r2
str r1,[r0]

;STEP18 - AN EXTENDED MODE REGISTER SET (EMRS1) IS ISSUED TO ENABLE OCD EXIT
ldr r0,=MPDDRC_MR ;Set second CBR
mov r1,#0x00000005
str r1,[r0]
ldr r0,=(SDRAM_START+0x06000000) ;
mov r1,#0x00000000
str r1,[r0]
;delay
mov r0,#0x200
BL delay

;STEP19 - A MODE NORMAL COMMAND IS PROVIDED.
; PROGRAM THE NORMAL MODE INTO MODE REGISTER
ldr r0,=MPDDRC_MR ;Set second CBR
mov r1,#0x00000000
str r1,[r0]
ldr r0,=SDRAM_START ;
mov r1,#0x00000000
str r1,[r0]

;STEP20 - PERFORM A WRITE ACCESS TO ANY DDRRAM ADRES
ldr r0,=SDRAM_START ;
mov r1,#0x00000000
str r1,[r0]

;STEP21 - WRITE THE REFRESH RATE INTO THE REFRESH TIMER REGISTER
ldr r0,=MPDDRC_RTR
ldr r1,=0x00000411
str r1,[r0]
;delay
mov r0,#0x20000
BL delay

;THAT'S IT !

ldr r3,=0x20000010
ldr r1,=0x00000000
ramtstnew ldr r0,=0x20000000
ramtst str r1,[r0],#+4
cmp r0,r3
bne ramtst

ldr r0,=0x20000000
ramtst2 ldr r2,[r0],#+4
cmp r2,r1
bne loop
cmp r0,r3
bne ramtst2

mov r0,r1
bl putchar
add r1,r1,#0x00000001
b ramtstnew

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