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boot from sdmmc1 and access nand on IOSET2

Posted: Mon Apr 16, 2018 1:25 am
by bmpenrod
I'm bringing up a custom board based on the SAMA5D27 SIP and a very much stripped down SAMA5D27_SOM1_EK reference design. I'm only using ethernet and uarts from that design. Since there is no nand on the SAMA5D27_SOM1_EK, I copied the device tree settings from the SAMA5D2_PTC_EK design, except that I connected the nand chip to the IOSET2 pin group. I even used the same Micron 512MB flash chip used in the SAMA5D2_PTC_EK, which happens to be the one we are currently using in an existing embedded linux product.

I also have the SDMMC1 pins connected to a uSD interface, exactly like the SAMA5D27_SOM1_EK. Since the ROMBoot defaults to booting from SDMMC1, I have made no changes to the default boot configuration register (i.e. have not burned the fuse register or used the BUREGs). This works perfectly, and I can use at91bootstrap to load the linux kernel and bring up my system just fine. The problem is that the nand chip is not detected properly by the kernel as it is booting. It reads incorrect manufacturer and chip ids and ultimately decides that no nand chip is found. I get this behavior on more than one board, so it is not likely a hardware assembly issue.

I know that there is one pin that is used by both the nand ioset2 and sdmmc1 pin groups: the nand RDY/BUSY pin is the same as D3 on the sdmmc1 interface. I also know that this pin is often not used in a nand interface, so I have not hooked it up to the nand chip.

As a test, I have also configured at91bootstrap to access nand, again based on the SAMA5D2_PTC_EK as a reference for modifying the at91bootstrap source to allow booting linux from nand on the SAMA5D27_SOM1_EK. (While making the code mods, I saw that the nand RDY/BUSY pin is not used at all by at91bootstrap.) Still, when loading at91bootstrap from my sdmmc1 card, it is also unable to read the nand device ids and gives up.

I guess my question is: Is it possible to have sdmmc1 and nand on ioset2 configured at the same time? If not, I will give up and go down the SAM-BA route to burn the flash, assuming I can get that to recognize the chip. My intent was to boot linux using sdmmc1 and then use the mtd tools to burn everything into the nand partitions.

Re: boot from sdmmc1 and access nand on IOSET2

Posted: Wed Apr 18, 2018 1:52 am
by blue_z
bmpenrod wrote:I'm bringing up a custom board based on the SAMA5D27 SIP
You neglect to mention the specific versions of AT91Bootstrap and Linux kernel that you are using.
You neglect to show what driver code modifications you may have made and what your board's Device Tree contains.

bmpenrod wrote:This works perfectly, and I can use at91bootstrap to load the linux kernel and bring up my system just fine. The problem is that the nand chip is not detected properly by the kernel as it is booting.
You're contradicting yourself.
If something works "perfectly" and/or is "just fine", then how can there be a "problem"?
bmpenrod wrote:I get this behavior on more than one board, so it is not likely a hardware assembly issue.
That's illogical reasoning.
You've provided zero information to eliminate any causes.

bmpenrod wrote:I also know that this pin is often not used in a nand interface, so I have not hooked it up to the nand chip.
I don't know the accuracy of your claim, but I assume that it's possible when the NAND chip is connected directly to the processor interface, i.e. there is no NFC.
I do assume that you are not privy to the internals workings of the Atmel NFC, meaning that you don't know what happens when the NANDRDY input of the NFC is left floating.

bmpenrod wrote:As a test, I have also configured at91bootstrap to access nand, again based on the SAMA5D2_PTC_EK as a reference for modifying the at91bootstrap source to allow booting linux from nand on the SAMA5D27_SOM1_EK.
The SAMA5D27-SOM1-EK1 has no NAND flash (according to its User Guide).
Are you conflating your board with the Microchip/Atmel board?

bmpenrod wrote:Is it possible to have sdmmc1 and nand on ioset2 configured at the same time?
If you can avoid pin conflicts, then it should be possible.
Apparently you have overlooked the alternate NANDRDY input on PD8.
And you probably have other issues that inhibit NAND access.

Regards

Can't read nand mfr & chip ids for Micron MT29F4G16ABADAWP

Posted: Wed Apr 18, 2018 11:20 pm
by bmpenrod
Re-posting this because moderator moved it to the products section of the forum, which I cannot access to either read or post for some reason...adding more detail as well.

Developing a custom board with SAMA5D27 SIP using SAMA5D27_SOM1_EK and SAMA5D2_PTC_EK reference designs as guides.

SAMA5D27_SOM1_EK has no NAND. SAMA5D2_PTC_EK has NAND, in fact schematic shows exactly same NAND I am using on my customer board.

I am connecting NAND to IOSET2 instead of IOSET1 as is in SAMA5D2_PTC_EK ref design. I'm doing this because I need to use a uSD card on SDMMC1 for initlal booting while I am getting nand figured out. I've done this before, nand is a pain in the ass.

Copied the nand related device tree stuff from at91-sama5d2_ptc_ek.dts to my modified at91-sama5d27_som1.dtsi and edited the nand pinctrl stuff to be IOSET2. Also, so as not to conflict with my SDMMC1 interface, I'm using the NANDRDY signal on PC8 instead of the normal IOSET2 pin, PA21.

Kernel is:
Linux version 4.9.75-linux4sam_5.7-XDC-330X-01637-g8f511fd-dirty (root@Linux9) (gcc version 4.9.4 (Linaro GCC 4.9-2017.01) ) #6 Thu Apr 12 18:52:49 UTC 2018

At this point, I am still booting the system from the SDMMC1 interface, and I expect to see the NAND flash probed, recognized and mtd partitions configured per the device tree. Unfortunately this is what the kernel says:

atmel_nand_nfc c0000000.nfc: NFC is probed.
atmel_nand 80000000.nand: Using dma0chan0 for DMA transfers.
nand: device found, Manufacturer ID: 0xff, Chip ID: 0x2c
nand: Unknown 80000000.nand
nand: bus width 16 instead 8 bit
nand: No NAND device found

It appears that the simple act of reading the device ids doesn't work. I know that the Micron chip I am using has Mfr ID = 2c, and Chip ID = dc. It sort of looks like the NFC is reading garbage on the first byte, then reads the Mfr ID into the Chip ID on the second read. However, the value displayed for the Chip ID could be just coincidentally the correct value for the Manufacturer ID.

Maybe I'm missing something in the device tree setup...? I have verified this behavior on multiple boards, and have continuity-checked the nand to sama5d27 sip wiring using a bareboard to verify it matches the schematic. Not much more to do, only a handful of wires to deal with.

Here is nand device tree stuff from sama5d2.dtsi:

nand0: nand@80000000 {
compatible = "atmel,sama5d2-nand";
#address-cells = <1>;
#size-cells = <1>;
ranges;
reg = < /* EBI CS3 */
0x80000000 0x08000000
/* SMC PMECC regs */
0xf8014070 0x00000490
/* SMC PMECC Error Location regs */
0xf8014500 0x00000200
/* ROM Galois tables */
0x00040000 0x00018000
>;
interrupts = <17 IRQ_TYPE_LEVEL_HIGH 6>;
atmel,nand-addr-offset = <21>;
atmel,nand-cmd-offset = <22>;
atmel,nand-has-dma;
atmel,has-pmecc;
atmel,pmecc-lookup-table-offset = <0x0 0x8000>;
status = "okay";

nfc@c0000000 {
compatible = "atmel,sama5d3-nfc";
#address-cells = <1>;
#size-cells = <1>;
reg = < /* NFC Command Registers */
0xc0000000 0x08000000
/* NFC HSMC regs */
0xf8014000 0x00000070
/* NFC SRAM banks */
0x00100000 0x00100000
>;
clocks = <&hsmc_clk>;
atmel,write-by-sram;
};
};

Here is nand stuff in at91-sama5d27_som1.dtsi:

nand0: nand@80000000 {
nand-bus-width = <8>;
nand-ecc-mode = "hw";
nand-on-flash-bbt;
atmel,has-pmecc;
atmel,pmecc-cap = <4>;
atmel,pmecc-sector-size = <512>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_nand_default>;
status = "okay";

at91bootstrap@0 {
label = "bootstrap";
reg = <0x00000000 0x00040000>; /* 256k, mtd0 */
};

bootloader@40000 {
label = "bootloader";
reg = <0x00040000 0x000c0000>; /* 768k, mtd1 */
};

bootloaderenv@0x100000 {
label = "bootloader env";
reg = <0x00100000 0x00040000>; /* 256k, mtd2 */
};

bootloaderenvred@0x140000 {
label = "bootloader env redundant";
reg = <0x00140000 0x00040000>; /* 256k, mtd3 */
};

dtb@180000 {
label = "device tree";
reg = <0x00180000 0x00080000>; /* 512k, mtd4 */
};
kernel_1@800000 {
label = "kernel_1";
reg = <0x00800000 0x00600000>; /* 6M, mtd6 */
};
rootfs_0@E00000 {
label = "rootfs_0";
reg = <0x00E00000 0x04000000>; /* 64M, mtd7 */
};
rootfs_1@4E00000 {
label = "rootfs_1";
reg = <0x04E00000 0x04000000>; /* 64M, mtd8 */
};
boot@8E00000 {
label = "boot";
reg = <0x08E00000 0x01000000>; /* 16M, mtd9 */
};
home@9E00000 {
label = "home";
reg = <0x09E00000 0x04000000>; /* 64M, mtd10 */
};
logs@DE00000 {
label = "home";
reg = <0x0DE00000 0x12200000>; /* 300M, mtd11 */
};
};

And the pinctrl stuff in at91-sama5d27_som1.dtsi:

pinctrl_nand_default: nand_default {
pinmux = <PIN_PA12__NRD_NANDOE>,
<PIN_PA8__NWE_NANDWE>,
<PIN_PA0__D0>,
<PIN_PA1__D1>,
<PIN_PA2__D2>,
<PIN_PA3__D3>,
<PIN_PA4__D4>,
<PIN_PA5__D5>,
<PIN_PA6__D6>,
<PIN_PA7__D7>,
<PIN_PA10__A21_NANDALE>,
<PIN_PA11__A22_NANDCLE>,
<PIN_PC8__NANDRDY>,
<PIN_PA9__NCS3>;
bias-pull-up;
};

Re: Can't read nand mfr & chip ids for Micron MT29F4G16ABADAWP

Posted: Wed Apr 18, 2018 11:23 pm
by bmpenrod
Correction: The chip is MT29F4G08ABADAWP, not the MT29F4G16ABADAWP.

Re: Can't read nand mfr & chip ids for Micron MT29F4G16ABADAWP

Posted: Thu Apr 19, 2018 10:18 pm
by bmpenrod
OK. Now looks like there is a serious incompatibility with linux kernel nand driver with this Micron MT29F4G08ABADA chip. The chip is ONFI 1.0 compliant.

Previously I noticed that the MFR ID seemed to be appearing in the Chip ID field during kernel boot. I suspected that possibly the first read of the chip after chip reset in nand_base.c was wrong. So I did a simple hack to do a dummy read of the chip first before letting the driver do its normal thing. Now the first 5 bytes are read correctly per the Micron datasheet and the chip is identified correctly. But we're not out of the woods yet:

atmel_nand_nfc c0000000.nfc: NFC is probed.
atmel_nand 80000000.nand: Using dma0chan0 for DMA transfers.
nand: First 8 bytes on 2nd Read: 2c dc 90 95 56 00 00 00
nand: device found, Manufacturer ID: 0x2c, Chip ID: 0xdc
nand: Micron NAND 512MiB 3,3V 8-bit
nand: 512 MiB, SLC, erase size: 128 KiB, page size: 2048, OOB size: 64
atmel_nand 80000000.nand: Use On Flash BBT
atmel_nand 80000000.nand: can't detect min. ECC, assume 2 bits in 512 bytes
atmel_nand 80000000.nand: Initialize PMECC params, cap: 4, sector: 512
atmel_nand 80000000.nand: invalid resource
atmel_nand 80000000.nand: Using NFC Sram read and write
atmel_nand 80000000.nand: PMECC: Timeout to get error status.
atmel_nand 80000000.nand: PMECC: Timeout to get error status.
atmel_nand 80000000.nand: PMECC: Timeout to get error status.
atmel_nand 80000000.nand: PMECC: Timeout to get error status.
Bad block table not found for chip 0
atmel_nand 80000000.nand: PMECC: Timeout to get error status.
atmel_nand 80000000.nand: PMECC: Timeout to get error status.
atmel_nand 80000000.nand: PMECC: Timeout to get error status.
atmel_nand 80000000.nand: PMECC: Timeout to get error status.
Bad block table not found for chip 0
Scanning device for bad blocks
nand_bbt: error while erasing BBT block -5
nand_bbt: error -5 while marking block 4095 bad
nand_bbt: error while erasing BBT block -5
nand_bbt: error -5 while marking block 4094 bad
nand_bbt: error while erasing BBT block -5
nand_bbt: error -5 while marking block 4093 bad
nand_bbt: error while erasing BBT block -5
nand_bbt: error -5 while marking block 4092 bad
No space left to write bad block table
nand_bbt: error while writing bad block table -28

Since this exact same chip is shown on the sama5d2_ptc_ek schematic, I'm wondering how it is working??? Clearly at this point, the hardware interconnect between the SAMA5D27 SIP and the nand chip appears functional, but there are other problems.

There must be more to know about the device tree interface--or bugs in the NFC driver?