how to Cache lockdown?

Discussion around products based on ARM Cortex-A5 core.

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jinxin16897123
Posts: 1
Joined: Mon Sep 19, 2016 4:04 am

how to Cache lockdown?

Mon Sep 19, 2016 4:12 am

In ARM cortex-a V7 PDF,
cache lockdown was implemention defined.
in sama5d3 pdf, cache lockdown was support,
is there any operation to lockdown cache?
thank you.
blue_z
Location: USA
Posts: 1560
Joined: Thu Apr 19, 2007 10:15 pm

Re: how to Cache lockdown?

Mon Sep 19, 2016 9:11 pm

jinxin16897123 wrote:In ARM cortex-a V7 PDF, ...
ARM Cortex-A is a group of processor cores.
ARMv7 is a processor architecture.
But "ARM cortex-a V7" is a ambiguous and/or meaningless mashup of names.
So exactly what document are you looking at?
jinxin16897123 wrote:in sama5d3 pdf, cache lockdown was support,
is there any operation to lockdown cache?
Which cache?

The Atmel SAMA5D line of SoCs all use the ARM Cortex-A5 core.
The ARM Cortex-A5 Technical Reference Manual, Revision: r0p1, clearly states that L1 instruction cache controller has no lockdown support.
The TRM makes no mention of it, but you can probably assume that L1 data cache controller also has no lockdown support.
If your board has an external L2 cache controller, i.e. the PL310 Cache Controller, then it's another story.

Regards

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