Endian mixups with GDB disassembler on SAMA5D2B-XULT

Discussion around products based on ARM Cortex-A5 core.

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dandersonee
Posts: 3
Joined: Fri Aug 19, 2016 6:31 am

Endian mixups with GDB disassembler on SAMA5D2B-XULT

Fri Aug 19, 2016 7:40 am

Anyone run into endian problems with GDB disassembler and have any suggestions?
I have attached logs from the getting_started demo from the Atmel Software Package
Note that when disassembling the first time, the bytes are all byteswapped and so the disassembler misinterprets the code.
When I dump the memory, it doesn’t match what the disassembler showed for the byte order.
When I turned off code-cache in gdb, the disassembler read things in the correct order and the disassembly matches the source
When I dumped memory, it is unchanged
The endian bit of the cpsr register is 0 (little endian) in both cases.
When code-cache is on, the GDB Server logs show it reads 64 bytes from the target at a time
When code cache is off the GDB server logs show it reads every word as a 32-bit word then reads each of the bytes separately.

Development board: SAMA5D2B-XULT (uses SAMA5D27B )
Using on-board EDBG with the updated firmware (5/3/16) from Segger
Jumpers BOOT_DIS, DEBUG_DIS closed
Jumper EDBG_DIS open
Connect J23 A5-USB-A to PC over USB
Connect J14 EDBG to PC over USB
Platform: Windows 10 64-bit
Atmel Software Package 2.4
Arm-gnu-toolchain-5.4 arm-none-eabi
Segger J-Link 6.00g
Segger J-Link GDB SERVER 6.00g
Start Segger J-Link GDB Server with options: -select USB -device ATSAMA5D27 -if JTAG -speed auto -noir
$ cd c:/devat/atmel-software-package-2.4/examples/getting_started
$ make TARGET=sama5d2-xplained VARIANT=ddram debug
GNU gdb (GNU Tools for ARM Embedded Processors) 7.10.1.20160616-cvs
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and "show warranty" for details.
This GDB was configured as "--host=i686-w64-mingw32 --target=arm-none-eabi".
Type "show configuration" for configuration details.
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Reading symbols from C:/devat/atmel-software-package-2.4/examples/getting_started/build/getting-started_sama5d2-xplained_ddram.elf...expanding to full symbols...done.
0x00218a14 in ?? ()
Writing register (F0 = 0x000000D3)
Writing CP15 register (1,0,0,0 = 0x00C50078)
Writing register (#41 = 0x00000000)
Writing register (#42 = 0x00000000)
Writing register (#43 = 0x00000000)
Writing register (#44 = 0x00000000)
Writing register (#45 = 0x00000000)
Writing register (#46 = 0x00000000)
Writing register (#47 = 0x00000000)
Writing register (#48 = 0x00000000)
Writing register (#49 = 0x00000000)
Writing register (#50 = 0x00000000)
Writing register (#51 = 0x00000000)
Writing register (#55 = 0x00000000)
Writing register (#56 = 0x00000000)
Writing register (#57 = 0x00000000)
Writing register (#58 = 0x00000000)
Writing register (#59 = 0x00000000)
Writing register (#60 = 0x00000000)
Writing register (#52 = 0x00000000)
Writing register (#53 = 0x00000000)
Writing register (#54 = 0x00000000)
Writing register (R0 = 0x00000000)
Writing register (R1 = 0x00000000)
Writing register (R2 = 0x00000000)
Writing register (R3 = 0x00000000)
Writing register (R4 = 0x00000000)
Writing register (R5 = 0x00000000)
Writing register (R6 = 0x00000000)
Writing register (R7 = 0x00000000)
Writing register (#34 = 0x00000000)
Writing register (#35 = 0x00000000)
Writing register (#36 = 0x00000000)
Writing register (#37 = 0x00000000)
Writing register (#38 = 0x00000000)
Writing register (#39 = 0x00000000)
Writing register (#40 = 0x00000000)
Loading section .fixed0, size 0x5c84 lma 0x200000
Loading section .ARM.exidx, size 0x8 lma 0x205ca0
Start address 0x20003c, load size 23692
Transfer rate: 14 KB/sec, 3384 bytes/write.
Writing register (PC = 0x00200000)
Writing register (PC = 0x00200000)

Program received signal SIGTRAP, Trace/breakpoint trap.
0x00200378 in ?? ()
Writing register (#41 = 0x00000000)
Writing register (#42 = 0x00000000)
Writing register (#43 = 0x00000000)
Writing register (#44 = 0x00000000)
Writing register (#45 = 0x00000000)
Writing register (#46 = 0x00000000)
Writing register (#47 = 0x00000000)
Writing register (#48 = 0x00000000)
Writing register (#49 = 0x00000000)
Writing register (#50 = 0x00000000)
Writing register (#51 = 0x00000000)
Writing register (#55 = 0x00000000)
Writing register (#56 = 0x00000000)
Writing register (#57 = 0x00000000)
Writing register (#58 = 0x00000000)
Writing register (#59 = 0x00000000)
Writing register (#60 = 0x00000000)
Writing register (#52 = 0x00000000)
Writing register (#53 = 0x00000000)
Writing register (#54 = 0x00000000)
Writing register (R0 = 0x00000000)
Writing register (R1 = 0x00000000)
Writing register (R2 = 0x00000000)
Writing register (R3 = 0x00000000)
Writing register (R4 = 0x00000000)
Writing register (R5 = 0x00000000)
Writing register (R6 = 0x00000000)
Writing register (R7 = 0x00000000)
Writing register (#34 = 0x00000000)
Writing register (#35 = 0x00000000)
Writing register (#36 = 0x00000000)
Writing register (#37 = 0x00000000)
Writing register (#38 = 0x00000000)
Writing register (#39 = 0x00000000)
Writing register (#40 = 0x00000000)
Loading section .fixed0, size 0xc8c4 lma 0x20000000
Loading section .ARM.exidx, size 0x8 lma 0x2000c8c4
Loading section .relocate, size 0x3c lma 0x2000c8cc
Start address 0x20000000, load size 51464
Transfer rate: 14 KB/sec, 3430 bytes/write.
Writing register (PC = 0x20000000)
PC = 20000000, CPSR = E00000D3 (SVC mode, ARM FIQ dis. IRQ dis.)
R0 = 00000000, R1 = 00000000, R2 = 00000000, R3 = 00000000
R4 = 00000000, R5 = 00000000, R6 = 00000000, R7 = 00000000
USR: R8 =00000000, R9 =00000000, R10=00000000, R11 =00000000, R12 =00000000
R13=00000000, R14=00000000
FIQ: R8 =00000000, R9 =00000000, R10=00000000, R11 =00000000, R12 =00000000
R13=00000000, R14=00000000, SPSR=00000000
SVC: R13=00000000, R14=00000000, SPSR=00000000
ABT: R13=00000000, R14=00000000, SPSR=00000000
IRQ: R13=00000000, R14=00000000, SPSR=00000000
UND: R13=00000000, R14=00000000, SPSR=00000000

(gdb) disassemble/rm 0x20000000,+40
Dump of assembler code from 0x20000000 to 0x20000028:
183 ldr pc, =resetHandler
=> 0x20000000 <entry+0>: e5 9f f0 fc ldc2l 15, cr9, [r0], #916 ; 0x394

184 ldr pc, =resetHandler
0x20000004 <entry+4>: e5 9f f0 f8 ; <UNDEFINED> instruction: 0xf8f09fe5

185 ldr pc, =resetHandler
0x20000008 <entry+8>: e5 9f f0 f4 ; <UNDEFINED> instruction: 0xf4f09fe5

186 ldr pc, =resetHandler
0x2000000c <entry+12>: e5 9f f0 f0 ; <UNDEFINED> instruction: 0xf0f09fe5

187 ldr pc, =resetHandler
0x20000010 <entry+16>: e5 9f f0 ec ldcl 15, cr9, [r0], #916 ; 0x394

188 ldr pc, =resetHandler
0x20000014 <entry+20>: e5 9f f0 ff ; <UNDEFINED> instruction: 0xfff09fe5

189 ldr pc, =resetHandler
0x20000018 <entry+24>: e5 9f f0 e4 ldrbt r9, [r0], #4069 ; 0xfe5

190 ldr pc, =resetHandler
0x2000001c <entry+28>: e5 9f f0 e0 rscs r9, r0, r5, ror #31

191
192 resetHandler:
193
194 cpsie a
0x20000020 <resetHandler+0>: f1 08 01 00 strdeq r0, [r1], -r1

195
196 /* Set up the fast interrupt stack pointer */
197
198 mrs r0, CPSR
0x20000024 <resetHandler+4>: e1 0f 00 00 andeq r0, r0, r1, ror #31

End of assembler dump.

(gdb) x/20xw 0x20000000
0x20000000 <entry>: 0xe59ff0fc 0xe59ff0f8 0xe59ff0f4 0xe59ff0f0
0x20000010 <entry+16>: 0xe59ff0ec 0xe59ff0e8 0xe59ff0e4 0xe59ff0e0
0x20000020 <resetHandler>: 0xf1080100 0xe10f0000 0xe3c0001f 0xe3800011
0x20000030 <resetHandler+16>: 0xe121f000 0xe59fd0cc 0xe3cdd007 0xe3c0001f
0x20000040 <resetHandler+32>: 0xe3800012 0xe121f000 0xe59fd0bc 0xe3cdd007

(gdb) i r cpsr
cpsr 0xe00000d3 3758096595

(gdb) set code-cache off

(gdb) disassemble/rm 0x20000000,+40
Dump of assembler code from 0x20000000 to 0x20000028:
183 ldr pc, =resetHandler
=> 0x20000000 <entry+0>: fc f0 9f e5 ldr pc, [pc, #252] ; 0x20000104 <resetHandler+228>

184 ldr pc, =resetHandler
0x20000004 <entry+4>: f8 f0 9f e5 ldr pc, [pc, #248] ; 0x20000104 <resetHandler+228>

185 ldr pc, =resetHandler
0x20000008 <entry+8>: f4 f0 9f e5 ldr pc, [pc, #244] ; 0x20000104 <resetHandler+228>

186 ldr pc, =resetHandler
0x2000000c <entry+12>: f0 f0 9f e5 ldr pc, [pc, #240] ; 0x20000104 <resetHandler+228>

187 ldr pc, =resetHandler
0x20000010 <entry+16>: ec f0 9f e5 ldr pc, [pc, #236] ; 0x20000104 <resetHandler+228>

188 ldr pc, =resetHandler
0x20000014 <entry+20>: e8 f0 9f e5 ldr pc, [pc, #232] ; 0x20000104 <resetHandler+228>

189 ldr pc, =resetHandler
0x20000018 <entry+24>: e4 f0 9f e5 ldr pc, [pc, #228] ; 0x20000104 <resetHandler+228>

190 ldr pc, =resetHandler
0x2000001c <entry+28>: e0 f0 9f e5 ldr pc, [pc, #224] ; 0x20000104 <resetHandler+228>

191
192 resetHandler:
193
194 cpsie a
0x20000020 <resetHandler+0>: 00 01 08 f1 cpsie a

195
196 /* Set up the fast interrupt stack pointer */
197
198 mrs r0, CPSR
0x20000024 <resetHandler+4>: 00 00 0f e1 mrs r0, CPSR

End of assembler dump.

(gdb) x/20xw 0x20000000
0x20000000 <entry>: 0xe59ff0fc 0xe59ff0f8 0xe59ff0f4 0xe59ff0f0
0x20000010 <entry+16>: 0xe59ff0ec 0xe59ff0e8 0xe59ff0e4 0xe59ff0e0
0x20000020 <resetHandler>: 0xf1080100 0xe10f0000 0xe3c0001f 0xe3800011
0x20000030 <resetHandler+16>: 0xe121f000 0xe59fd0cc 0xe3cdd007 0xe3c0001f
0x20000040 <resetHandler+32>: 0xe3800012 0xe121f000 0xe59fd0bc 0xe3cdd007

(gdb) i r cpsr
cpsr 0xe00000d3 3758096595
tsvoipio
Posts: 53
Joined: Wed Aug 19, 2015 9:44 pm

Re: Endian mixups with GDB disassembler on SAMA5D2B-XULT

Sat Aug 20, 2016 7:09 pm

It seems to me that you're attempting to feed 32 bit ARM code to a Cortex A5 processor, which eats Thumb2 code.

Did you tell the compiler and linker that the target is a Cortex processor?
dandersonee
Posts: 3
Joined: Fri Aug 19, 2016 6:31 am

Re: Endian mixups with GDB disassembler on SAMA5D2B-XULT

Sun Aug 21, 2016 4:45 am

Thanks for the idea but I dont think that is it.
The specific device ATSAMA5D27 was passed to the GDBServer at startup.
Per the Atmel SAMA5D2 datasheet:
The Cortex-A5 processor implements the ARMv7 architecture and
runs 32-bit ARM instructions, 16-bit and 32-bit Thumb instructions, and 8-bit Java™ byte codes in Jazelle® state.
The cstartup.S file from Atmel where this code is built from also explicitly has the .arm assembler directive.

It appears to be when gdb is reading memory from the device a 32-bit word at a time, it is storing it in a local buffer in the correct byte order, but when it tries to do a cache line read of 64-bytes, gdb is storing it in its buffer in the wrong byte order?
blue_z
Location: USA
Posts: 1508
Joined: Thu Apr 19, 2007 10:15 pm

Re: Endian mixups with GDB disassembler on SAMA5D2B-XULT

Mon Aug 22, 2016 10:42 pm

dandersonee wrote:Anyone run into endian problems with GDB disassembler and have any suggestions?
...
Platform: Windows 10 64-bit
Presumably you're using Bash on Ubuntu on Windows.
FYI that is beta software, and therefore a questionable choice for a development host.
There are a couple of reports related to gdb in the MS bug list,
At some point you will probably have to try to duplicate the issue using a real GNU (e.g. Linux) host to prove that the Windows host is not the cause or a contributing factor.

Regards
dandersonee
Posts: 3
Joined: Fri Aug 19, 2016 6:31 am

Re: Endian mixups with GDB disassembler on SAMA5D2B-XULT

Tue Aug 23, 2016 3:51 am

Thanks blue_z. I am not actually using Bash on Ubuntu on Windows. I had briefly thought about it but the Windows 10 Anniversary Update for the mainstream had not been released yet when I was doing this and I have only been using Windows Insider builds in a VM for playing around.

I am using Windows builds of tools, not trying to run Ubuntu builds of tools under Windows. I am also doing bare-metal builds (arm-none-eabi), not building for Linux or linking with Linux libraries. That said, instead of using Cygwin under Windows, I have been using bash (from Github) under Powershell to build the make files. I had been checking the GCC-arm-embedded, Atmel software package, the GNU/GDB, and Segger J-Link bug lists/updates. I will try to follow the WSL (“Bash on Windows”) issues also.

I was not sure if other people had only loaded and run the demo on the eval board (that works for me using gdb also) but maybe had not verified single step debugging or disassembly, or maybe bug fixes or improvements to one of the libraries or tools had broken what used to work. I had been trying to set this all up in Eclipse but have since backed off to try to run the official demo on the official eval board first to verify the tools.

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