MPDDRC Delay locked loop (DLL) settings

Discussion around products based on ARM Cortex-A5 core.

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Joined: Tue May 06, 2014 2:14 pm

MPDDRC Delay locked loop (DLL) settings

Mon Jul 07, 2014 9:06 am


in at91bootstrap I found a piece of code that configures the
programmable master/slave x/clk90 delay line offsets
(belongs to multi port DDR-SDRAM controller). The hard-coded offsets are explicitly switched off. Furthermore values for LPDDR and DDR memory are set differently. Now my question: Where do these values come from and what do they mean? The sama5d3 datasheet doesn't tell much about these settings.

Thanks in advance,

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