Chip Select Problems "SPI"

Discussion around product based on ARM Cortex M4 core.

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Iceberg
Posts: 4
Joined: Wed Jul 09, 2014 2:40 pm

Chip Select Problems "SPI"

Tue Oct 13, 2015 2:28 pm

Hi.

Can anyone tell me if it's possible to use NPCS1 on IO PB14, Peripheral A as Chip Select. And if so, How?

info:
- sam4sd32
- ASF driver

Regards Ib
Iceberg
Posts: 4
Joined: Wed Jul 09, 2014 2:40 pm

Re: Chip Select Problems "SPI"

Wed Oct 14, 2015 10:42 am

i think it's the current peripheral setting that's the problem.
if i use: (Page 706 datasheet)
SPI->SPI_MR |= 0 << 1; // PS = 0 Fixed Peripheral Select
SPI->SPI_MR |= 0x1 << 16; // then PCS = SPI_CSR[1]? regtestCSR1 = 0x10400880

and i still cant see where to hook up PB14 to CS1
Iceberg
Posts: 4
Joined: Wed Jul 09, 2014 2:40 pm

Re: Chip Select Problems "SPI"

Wed Oct 14, 2015 1:54 pm

Problem solved!

Code: Select all

#define SPI_CHIP_SEL1			1    //Use SPI Chip Select 1 (SPI_NPCS1_GPIO) for CS
#define SPI_CHIP_PCS1 spi_get_pcs(SPI_CHIP_SEL1)

Code: Select all

pio_configure_pin(SPI_NPCS1_PB14_GPIO, SPI_NPCS1_PB14_FLAGS);
	
spi_enable_clock(SPI_MASTER_BASE);
spi_disable(SPI_MASTER_BASE);
spi_reset(SPI_MASTER_BASE);
spi_set_lastxfer(SPI_MASTER_BASE);
spi_set_master_mode(SPI_MASTER_BASE);
spi_disable_mode_fault_detect(SPI_MASTER_BASE);
spi_set_peripheral_chip_select_value(SPI_MASTER_BASE, SPI_CHIP_PCS1);
spi_configure_cs_behavior(SPI, 1, SPI_CS_RISE_NO_TX);
spi_set_clock_polarity(SPI_MASTER_BASE, SPI_CHIP_SEL1, SPI_CLK_POLARITY);
spi_set_clock_phase(SPI_MASTER_BASE, SPI_CHIP_SEL1, SPI_CLK_PHASE);
spi_set_bits_per_transfer(SPI_MASTER_BASE, SPI_CHIP_SEL1, SPI_CSR_BITS_16_BIT);
spi_set_baudrate_div(SPI_MASTER_BASE, SPI_CHIP_SEL1,(sysclk_get_cpu_hz() / 15000000));
spi_set_transfer_delay(SPI_MASTER_BASE, SPI_CHIP_SEL1, SPI_DLYBS,SPI_DLYBCT);
spi_enable(SPI_MASTER_BASE);

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