TWI single byte transfer synchronisation

Discussion around product based on ARM Cortex M4 core.

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suprafluid
Posts: 2
Joined: Tue Jul 14, 2015 12:29 am

TWI single byte transfer synchronisation

Tue Jul 14, 2015 12:35 am

Hi all,

I am implementing a TWI connection to a quite sofisticated chip with lots of protocol overhead. The packages I have to read via TWI range from 16 bytes to some kBytes. The amount is calculated from the first bytes that contain the header information. I'm running my TWI access in an own thread, so I have time to wait for a single byte to complete by polling the status register. But on the other hand, due to the RTOS, the TWI reading thread is sometimes too slow to catch up with the end of a single byte transfer.

I found out that as soon as I start the TWI Rx by setting the start bit

Code: Select all

p_twi->TWI_CR = TWI_CR_START;
the SCL line starts sending clock cycles byte by byte withouth waiting untill my thread got time to read out the p_twi->TWI_RHR register.

Hence, it misses some transimtted chars. What can I do? Ok I could read first the header via PDC (16 bytes fixed size), then perform a stop, calculate the complete data size and then transfer again the whole frame with the calculated size, but this is wasted bus resource. I would need some kind of clock stretching, but on the MASTER(SAM) side...
Is there any possiblity to read byte by byte on the TWI without sending STOP/RESTART on the bus?


I think that this might also be the reason why other have sometimes reading errors over TWI, because they missed byte signal (RXRDY Bit) when TWI is clocking just too fast for the application to catch RXRDY.

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uint32_t twi_master_read(Twi *p_twi, twi_packet_t *p_packet)
This function from ASF will miss bytes if run within a multithreaded system without avoiding task switch while performing twi_master_read. Its internal while{} loop has to run at full speed with no interruption longer than a byte cycle on the TWI bus!

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