Chaining 2 16-bit timer counter

Discussion around product based on ARM Cortex M4 core.

Moderators: nferre, ncollot

yonghan
Posts: 4
Joined: Thu Oct 04, 2012 9:45 pm

Chaining 2 16-bit timer counter

Tue Sep 09, 2014 12:41 pm

Hi all,
I would like to chain 2 16-bit timer counter(TC) using SAM4SD16C.

For a single channel 16-bit TC, I have the configuration as below.

The purpose of TC is to capture the data for both falling(_dwCaptured_ra) and rising edge(_dwCaptured_rb) of the signal.

For clock source of master(TC0), it will be external clock source and it will be connected to external I/O signal for capture mode. 

For clock source of slave(TC1), it will be TIOA2, when it rolls over from 0xFFFF to 0x0000, TC1 will increase by 1 and becomes 0x0001. 

Currently, I am not sure on how could I get my both falling(_dwCaptured_ra) and rising edge(_dwCaptured_rb) of the signal after chaining 2 TC together whether it's still from rising/ falling edge of TC0(MASTER) or rising/falling edge of TC1(SLAVE).

Also, when it rolls over from 0xFFFF to 0x0000, how the TIOA2 would increase TC1.

Another question will be, should I connect any I/O signal to TC1(

Code: Select all

static void TcCaptureInitialize(void)
{
  //  volatile uint32_t dummy;
    /* Configure the PMC to enable the Timer Counter clock TC0 channel 2.*/
    pmc_enable_periph_clk(ID_TC2);
    /*  Disable TC clock */
    REG_TC0_CCR2 = TC_CCR_CLKDIS;
    /*  Disable interrupts */
    REG_TC0_IDR2 = 0xFFFFFFFF;
    /*  Clear status register */
   // dummy = REG_TC0_SR2;
    /*  Set channel 2 as capture mode */
    REG_TC0_CMR2 = (TC_CMR_TCCLKS_XC1    /* Clock Selection ; clock exterieur selectionnées*/
                   | TC_CMR_LDRA_RISING           /* RA Loading Selection: rising edge of TIOA */
                   | TC_CMR_LDRB_FALLING          /* RB Loading Selection: falling edge of TIOA */
                   | TC_CMR_ABETRG                /* External Trigger Selection: TIOA */
                   | TC_CMR_ETRGEDG_FALLING );    /* External Trigger Edge Selection: Falling edge */
				   




 pio_handler_set_priority(PIN_TC0_TIOA2_PIO, (IRQn_Type) PIN_TC0_TIOA2_ID, IRQ_PRIOR_PIO);
}

void TC2_Handler( void )
{
if ( (tc_get_status(TC, TC_CHANNEL_CAPTURE) & TC_SR_LDRBS) == TC_SR_LDRBS )
		{
			
			_dwCaptured_ra = REG_TC0_RA2 ;
			_dwCaptured_rb = REG_TC0_RB2 ;
			//printf("RA= %u ,       RB= %u \n\r",(unsigned int)_dwCaptured_ra, (unsigned int)_dwCaptured_rb );




			nbIT++;		 // nombre d'interruptions reçu de TC0
			// _dwCaptured_pulses++ ;
			//sauverDataRegistres();
		}
}
I have added some configurtions for chaining 2 16-bit TC below:

Please pin point me if you think that the configuration is not correct. In fact, I have tried but it didn't work.

Code: Select all

//  volatile uint32_t dummy;
    /* Configure the PMC to enable the Timer Counter clock TC0 channel 2.*/
    pmc_enable_periph_clk(ID_TC2);
	pmc_enable_periph_clk(ID_TC3);
    /*  Disable TC clock */
    REG_TC0_CCR2 = TC_CCR_CLKDIS;
	//REG_TC1_CCR0 = TC_CCR_CLKEN;
    /*  Disable interrupts */
    REG_TC0_IDR2 = 0xFFFFFFFF;
	REG_TC1_BMR= (TC_BMR_TC0XC0S_TIOA2);
    /*  Clear status register */
   // dummy = REG_TC0_SR2;
    /*  Set channel 2 as capture mode */
    REG_TC0_CMR2 = (TC_CMR_TCCLKS_XC1    /* Clock Selection ; clock exterieur selectionnées*/
                   | TC_CMR_LDRA_RISING           /* RA Loading Selection: rising edge of TIOA */
                   | TC_CMR_LDRB_FALLING          /* RB Loading Selection: falling edge of TIOA */
                   | TC_CMR_ABETRG                /* External Trigger Selection: TIOA */
                   | TC_CMR_ETRGEDG_FALLING );    /* External Trigger Edge Selection: Falling edge */
				   
	REG_TC1_CMR0 = (TC_CMR_TCCLKS_XC0    /* Clock Selection ; clock exterieur selectionnées*/
					| TC_CMR_LDRA_RISING           /* RA Loading Selection: rising edge of TIOA */
					| TC_CMR_LDRB_FALLING          /* RB Loading Selection: falling edge of TIOA */
					| TC_CMR_ABETRG                /* External Trigger Selection: TIOA */
					| TC_CMR_ETRGEDG_FALLING );    /* External Trigger Edge Selection: Falling edge */
	
	
	
	REG_TC0_BCR = TC_BCR_SYNC; 
	REG_TC1_BCR = TC_BCR_SYNC;   





Thank you.

Return to “SAM4 Cortex-M4 MCU”

Who is online

Users browsing this forum: No registered users and 2 guests