Internal Flash & Internal ROM read write ?

Microchip in-system programming solution: SAM-BA

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1980best
Posts: 3
Joined: Mon Jul 05, 2010 3:50 pm

Internal Flash & Internal ROM read write ?

Tue Jul 06, 2010 7:45 am

Internal Memory read writing
AT91SAM7SE512.h ??
AT91_REG AIC_ISR; // Interrupt Status Register
.............................................................................................
/ *****************************************************************************
// SOFTWARE API DEFINITION FOR Memory Controller Interface
// *****************************************************************************
typedef struct _AT91S_MC {
AT91_REG MC_RCR; // MC Remap Control Register
AT91_REG MC_ASR; // MC Abort Status Register
AT91_REG MC_AASR; // MC Abort Address Status Register
AT91_REG Reserved0[1]; //
AT91_REG MC_PUIA[16]; // MC Protection Unit Area
AT91_REG MC_PUP; // MC Protection Unit Peripherals
AT91_REG MC_PUER; // MC Protection Unit Enable Register
AT91_REG Reserved1[2]; //
AT91_REG MC0_FMR; // MC Flash Mode Register
AT91_REG MC0_FCR; // MC Flash Command Register
AT91_REG MC0_FSR; // MC Flash Status Register
AT91_REG MC0_VR; // MC Flash Version Register
AT91_REG MC1_FMR; // MC Flash Mode Register
AT91_REG MC1_FCR; // MC Flash Command Register
AT91_REG MC1_FSR; // MC Flash Status Register
AT91_REG MC1_VR; // MC Flash Version Register
} AT91S_MC, *AT91PS_MC;
.......................................................................................................
/ -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register --------
#define AT91C_MC_RCB ((unsigned int) 0x1 << 0) // (MC) Remap Command Bit
// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register --------
#define AT91C_MC_UNDADD ((unsigned int) 0x1 << 0) // (MC) Undefined Addess Abort Status
#define AT91C_MC_MISADD ((unsigned int) 0x1 << 1) // (MC) Misaligned Addess Abort Status
#define AT91C_MC_MPU ((unsigned int) 0x1 << 2) // (MC) Memory protection Unit Abort Status
#define AT91C_MC_ABTSZ ((unsigned int) 0x3 << 8) // (MC) Abort Size Status
#define AT91C_MC_ABTSZ_BYTE ((unsigned int) 0x0 << 8) // (MC) Byte
#define AT91C_MC_ABTSZ_HWORD ((unsigned int) 0x1 << 8) // (MC) Half-word
#define AT91C_MC_ABTSZ_WORD ((unsigned int) 0x2 << 8) // (MC) Word
#define AT91C_MC_ABTTYP ((unsigned int) 0x3 << 10) // (MC) Abort Type Status
#define AT91C_MC_ABTTYP_DATAR ((unsigned int) 0x0 << 10) // (MC) Data Read
#define AT91C_MC_ABTTYP_DATAW ((unsigned int) 0x1 << 10) // (MC) Data Write
#define AT91C_MC_ABTTYP_FETCH ((unsigned int) 0x2 << 10) // (MC) Code Fetch
#define AT91C_MC_MST0 ((unsigned int) 0x1 << 16) // (MC) Master 0 Abort Source
#define AT91C_MC_MST1 ((unsigned int) 0x1 << 17) // (MC) Master 1 Abort Source
#define AT91C_MC_SVMST0 ((unsigned int) 0x1 << 24) // (MC) Saved Master 0 Abort Source
#define AT91C_MC_SVMST1 ((unsigned int) 0x1 << 25) // (MC) Saved Master 1 Abort Source
// -------- MC_PUIA : (MC Offset: 0x10) MC Protection Unit Area --------
#define AT91C_MC_PROT ((unsigned int) 0x3 << 0) // (MC) Protection
#define AT91C_MC_PROT_PNAUNA ((unsigned int) 0x0) // (MC) Privilege: No Access, User: No Access
#define AT91C_MC_PROT_PRWUNA ((unsigned int) 0x1) // (MC) Privilege: Read/Write, User: No Access
#define AT91C_MC_PROT_PRWURO ((unsigned int) 0x2) // (MC) Privilege: Read/Write, User: Read Only
#define AT91C_MC_PROT_PRWURW ((unsigned int) 0x3) // (MC) Privilege: Read/Write, User: Read/Write
#define AT91C_MC_SIZE ((unsigned int) 0xF << 4) // (MC) Internal Area Size
#define AT91C_MC_SIZE_1KB ((unsigned int) 0x0 << 4) // (MC) Area size 1KByte
#define AT91C_MC_SIZE_2KB ((unsigned int) 0x1 << 4) // (MC) Area size 2KByte
#define AT91C_MC_SIZE_4KB ((unsigned int) 0x2 << 4) // (MC) Area size 4KByte
#define AT91C_MC_SIZE_8KB ((unsigned int) 0x3 << 4) // (MC) Area size 8KByte
#define AT91C_MC_SIZE_16KB ((unsigned int) 0x4 << 4) // (MC) Area size 16KByte
#define AT91C_MC_SIZE_32KB ((unsigned int) 0x5 << 4) // (MC) Area size 32KByte
#define AT91C_MC_SIZE_64KB ((unsigned int) 0x6 << 4) // (MC) Area size 64KByte
#define AT91C_MC_SIZE_128KB ((unsigned int) 0x7 << 4) // (MC) Area size 128KByte
#define AT91C_MC_SIZE_256KB ((unsigned int) 0x8 << 4) // (MC) Area size 256KByte
#define AT91C_MC_SIZE_512KB ((unsigned int) 0x9 << 4) // (MC) Area size 512KByte
#define AT91C_MC_SIZE_1MB ((unsigned int) 0xA << 4) // (MC) Area size 1MByte
#define AT91C_MC_SIZE_2MB ((unsigned int) 0xB << 4) // (MC) Area size 2MByte
#define AT91C_MC_SIZE_4MB ((unsigned int) 0xC << 4) // (MC) Area size 4MByte
#define AT91C_MC_SIZE_8MB ((unsigned int) 0xD << 4) // (MC) Area size 8MByte
#define AT91C_MC_SIZE_16MB ((unsigned int) 0xE << 4) // (MC) Area size 16MByte
#define AT91C_MC_SIZE_64MB ((unsigned int) 0xF << 4) // (MC) Area size 64MByte
#define AT91C_MC_BA ((unsigned int) 0x3FFFF << 10) // (MC) Internal Area Base Address
// -------- MC_PUP : (MC Offset: 0x50) MC Protection Unit Peripheral --------
// -------- MC_PUER : (MC Offset: 0x54) MC Protection Unit Area --------
#define AT91C_MC_PUEB ((unsigned int) 0x1 << 0) // (MC) Protection Unit enable Bit

// *****************************************************************************
// SOFTWARE API DEFINITION FOR Embedded Flash Controller Interface
// *****************************************************************************
typedef struct _AT91S_EFC {
AT91_REG EFC_FMR; // MC Flash Mode Register
AT91_REG EFC_FCR; // MC Flash Command Register
AT91_REG EFC_FSR; // MC Flash Status Register
AT91_REG EFC_VR; // MC Flash Version Register
} AT91S_EFC, *AT91PS_EFC;

// -------- MC_FMR : (EFC Offset: 0x0) MC Flash Mode Register --------
#define AT91C_MC_FRDY ((unsigned int) 0x1 << 0) // (EFC) Flash Ready
#define AT91C_MC_LOCKE ((unsigned int) 0x1 << 2) // (EFC) Lock Error
#define AT91C_MC_PROGE ((unsigned int) 0x1 << 3) // (EFC) Programming Error
#define AT91C_MC_NEBP ((unsigned int) 0x1 << 7) // (EFC) No Erase Before Programming
#define AT91C_MC_FWS ((unsigned int) 0x3 << 8) // (EFC) Flash Wait State
#define AT91C_MC_FWS_0FWS ((unsigned int) 0x0 << 8) // (EFC) 1 cycle for Read, 2 for Write operations
#define AT91C_MC_FWS_1FWS ((unsigned int) 0x1 << 8) // (EFC) 2 cycles for Read, 3 for Write operations
#define AT91C_MC_FWS_2FWS ((unsigned int) 0x2 << 8) // (EFC) 3 cycles for Read, 4 for Write operations
#define AT91C_MC_FWS_3FWS ((unsigned int) 0x3 << 8) // (EFC) 4 cycles for Read, 4 for Write operations
#define AT91C_MC_FMCN ((unsigned int) 0xFF << 16) // (EFC) Flash Microsecond Cycle Number
// -------- MC_FCR : (EFC Offset: 0x4) MC Flash Command Register --------
#define AT91C_MC_FCMD ((unsigned int) 0xF << 0) // (EFC) Flash Command
#define AT91C_MC_FCMD_START_PROG ((unsigned int) 0x1) // (EFC) Starts the programming of th epage specified by PAGEN.
#define AT91C_MC_FCMD_LOCK ((unsigned int) 0x2) // (EFC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
#define AT91C_MC_FCMD_PROG_AND_LOCK ((unsigned int) 0x3) // (EFC) The lock sequence automatically happens after the programming sequence is completed.
#define AT91C_MC_FCMD_UNLOCK ((unsigned int) 0x4) // (EFC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
#define AT91C_MC_FCMD_ERASE_ALL ((unsigned int) 0x8) // (EFC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled.
#define AT91C_MC_FCMD_SET_GP_NVM ((unsigned int) 0xB) // (EFC) Set General Purpose NVM bits.
#define AT91C_MC_FCMD_CLR_GP_NVM ((unsigned int) 0xD) // (EFC) Clear General Purpose NVM bits.
#define AT91C_MC_FCMD_SET_SECURITY ((unsigned int) 0xF) // (EFC) Set Security Bit.
#define AT91C_MC_PAGEN ((unsigned int) 0x3FF << 8) // (EFC) Page Number
#define AT91C_MC_KEY ((unsigned int) 0xFF << 24) // (EFC) Writing Protect Key
// -------- MC_FSR : (EFC Offset: 0x8) MC Flash Command Register --------
#define AT91C_MC_SECURITY ((unsigned int) 0x1 << 4) // (EFC) Security Bit Status
#define AT91C_MC_GPNVM0 ((unsigned int) 0x1 << 8) // (EFC) Sector 0 Lock Status
#define AT91C_MC_GPNVM1 ((unsigned int) 0x1 << 9) // (EFC) Sector 1 Lock Status
#define AT91C_MC_GPNVM2 ((unsigned int) 0x1 << 10) // (EFC) Sector 2 Lock Status
#define AT91C_MC_GPNVM3 ((unsigned int) 0x1 << 11) // (EFC) Sector 3 Lock Status
#define AT91C_MC_GPNVM4 ((unsigned int) 0x1 << 12) // (EFC) Sector 4 Lock Status
#define AT91C_MC_GPNVM5 ((unsigned int) 0x1 << 13) // (EFC) Sector 5 Lock Status
#define AT91C_MC_GPNVM6 ((unsigned int) 0x1 << 14) // (EFC) Sector 6 Lock Status
#define AT91C_MC_GPNVM7 ((unsigned int) 0x1 << 15) // (EFC) Sector 7 Lock Status
#define AT91C_MC_LOCKS0 ((unsigned int) 0x1 << 16) // (EFC) Sector 0 Lock Status
#define AT91C_MC_LOCKS1 ((unsigned int) 0x1 << 17) // (EFC) Sector 1 Lock Status
#define AT91C_MC_LOCKS2 ((unsigned int) 0x1 << 18) // (EFC) Sector 2 Lock Status
#define AT91C_MC_LOCKS3 ((unsigned int) 0x1 << 19) // (EFC) Sector 3 Lock Status
#define AT91C_MC_LOCKS4 ((unsigned int) 0x1 << 20) // (EFC) Sector 4 Lock Status
#define AT91C_MC_LOCKS5 ((unsigned int) 0x1 << 21) // (EFC) Sector 5 Lock Status
#define AT91C_MC_LOCKS6 ((unsigned int) 0x1 << 22) // (EFC) Sector 6 Lock Status
#define AT91C_MC_LOCKS7 ((unsigned int) 0x1 << 23) // (EFC) Sector 7 Lock Status
#define AT91C_MC_LOCKS8 ((unsigned int) 0x1 << 24) // (EFC) Sector 8 Lock Status
#define AT91C_MC_LOCKS9 ((unsigned int) 0x1 << 25) // (EFC) Sector 9 Lock Status
#define AT91C_MC_LOCKS10 ((unsigned int) 0x1 << 26) // (EFC) Sector 10 Lock Status
#define AT91C_MC_LOCKS11 ((unsigned int) 0x1 << 27) // (EFC) Sector 11 Lock Status
#define AT91C_MC_LOCKS12 ((unsigned int) 0x1 << 28) // (EFC) Sector 12 Lock Status
#define AT91C_MC_LOCKS13 ((unsigned int) 0x1 << 29) // (EFC) Sector 13 Lock Status
#define AT91C_MC_LOCKS14 ((unsigned int) 0x1 << 30) // (EFC) Sector 14 Lock Status
#define AT91C_MC_LOCKS15 ((unsigned int) 0x1 << 31) // (EFC) Sector 15 Lock Status
// -------- EFC_VR : (EFC Offset: 0xc) EFC version register --------
#define AT91C_EFC_VERSION ((unsigned int) 0xFFF << 0) // (EFC) EFC version number
#define AT91C_EFC_MFN ((unsigned int) 0x7 << 16) // (EFC) EFC MFN
...............................................................................................


built-in memory to write and read operations is how. ???

please wait....

thank you..

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