SSC Endian Type Confusion

Discussion around product based on ARM Cortex M3 core.
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yun
Posts: 11
Joined: Mon Apr 13, 2015 9:10 pm

SSC Endian Type Confusion

Fri Jan 20, 2017 12:32 am

Hi guys,

Just having some confusion over what endian the SSC peripheral is outputting. I've configured it with a WM8731 codec (which I know is big endian [MSB first]) with an input word length of 32 bits. When I receive input from the codec, what am I getting out of the SSC peripheral? Is the data little endian or big endian? I can't seem to find a confirmation within the documentation.

Thanks!
blue_z
Location: USA
Posts: 1550
Joined: Thu Apr 19, 2007 10:15 pm

Re: SSC Endian Type Confusion

Fri Jan 20, 2017 3:22 am

yun wrote:Just having some confusion over what endian the SSC peripheral is outputting.
...
Is the data little endian or big endian?
Technically it's neither (endian being only a byte-order storage concept, and ambiguous for bit-serial communications).
But you can configure whether the most- or least-significant bit is transmitted first (MSBF bit in the SSC_TFMR register).

There is a (32-bit) shift register for the transmitted data.
Either the least-significant bit is shifted out first, followed by the adjacent bit, and the most-significant bit of the data is last, or the most-significant bit is shifted out first, followed by the adjacent bit, and the least-significant bit of the data is last.
Since the bit-order is always preserved within the transmission, the bit-order in the case of MSBF=0 does not resemble little-endian, but the other case, MSBF=1, the bit- and byte-order does resemble big-endian.

Regards
yun
Posts: 11
Joined: Mon Apr 13, 2015 9:10 pm

Re: SSC Endian Type Confusion

Fri Jan 20, 2017 11:43 pm

blue_z wrote:
yun wrote:Just having some confusion over what endian the SSC peripheral is outputting.
...
Is the data little endian or big endian?
Technically it's neither (endian being only a byte-order storage concept, and ambiguous for bit-serial communications).
But you can configure whether the most- or least-significant bit is transmitted first (MSBF bit in the SSC_TFMR register).

There is a (32-bit) shift register for the transmitted data.
Either the least-significant bit is shifted out first, followed by the adjacent bit, and the most-significant bit of the data is last, or the most-significant bit is shifted out first, followed by the adjacent bit, and the least-significant bit of the data is last.
Since the bit-order is always preserved within the transmission, the bit-order in the case of MSBF=0 does not resemble little-endian, but the other case, MSBF=1, the bit- and byte-order does resemble big-endian.

Regards
Thanks man! I just realized I could do that too haha.

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