Edge Triggered vs. Level Sensitive for Internal IRQs

Discussion about SAM7 Series and ARM7TDMI based products.

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pfilippi
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Edge Triggered vs. Level Sensitive for Internal IRQs

Wed Dec 08, 2004 9:30 pm

Dear AT91 Users,

you have probably all noticed that for internal IRQ sources coming from internal peripherals and going to the AIC, there is the possibility to configure the source type as Edge Triggered detection or Level Sensitive detection.

But what is the best one to use :?:

If we take the case that you only have one not nested interrupt at a time to manage in your application (I have a doubt... :shock: ), you can use the edge triggerred mode. But when there are severals IRQs to manage from one peripheral, by using the edge triggered way, you may lose IRQs if the first IRQ has not been treated fast enough to get another one from the same peripheral. The document attached with this topic gives you the explaination. To conclude there is no particular reason to use the edge triggered mode for internal IRQs.

repFichier/Document-294/Edge_Level_triggering.pdf
Last edited by pfilippi on Wed Jun 18, 2008 10:58 am, edited 2 times in total.
funkymunky
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Correct way of using PDC & USART with interrupts? (newB)

Sat Jan 15, 2005 8:49 am

Hi,

Im trying to use interrupts to send data out of the USART, employing the PDC. The chip im using is the AT91RM9200. I have configured the USART in loopback mode, sending and receiving data at the same USART. Ive configured the USART to interrupt whenever ENDRX is asserted.

I have a doubt regarding the way the ENDTX interrupt is asserted. According to a timing diagram i got from the AT91CDROM related to the USART and PDC (AT91RM9200-BasicPDC) ,the ENDRX interrupt is asserted when the transmit counter reaches zero, and stays high till TNCR (next counter) is written (i do that in the interrupt handler).

When the control enters the interrupt handler, interrupts will have been enabled, but ENDTX will still be high before a new value is written into TNCR..whats stopping more such interrupts from being asserted? is it the fact that the new interupt wil have the same priority as this one?

Also, i had interrupts enabled for ENDRX assertion..but i was getting multiple interrupts, as soon as i switched on the device..the problem went away only when i followed the foll procedure for setting the usart and the PDC:

first configure the USARt but dont enable RX\TX
configure the PDC, load the transfer\receive buffer pointers n counts
then enable RX and TX through the usart.
only at the end enable interrupt for ENDRX on the USART

but still, in the us_irq_handler if i do not disable ENDRX interrupts, im getting multiple interrupts. must i disable the interrupt? or will just putting in new values for the RX buffer in the PDC stop more interrupts?

:cry:

thanx in anticipation
Mayank
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stephan_cadene
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Sun Jan 16, 2005 10:08 am

Hi funkymunky,

The AT91RM9200 is a ARM9 based. Could you copy and past your topic in the ARM9 Based Sub-forum. Here is not the better sub-forum to speak about ARM9 but ARM7 Based and, particularly, SAM Series.

Thanks for your understanding
romanua
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Joined: Tue Feb 21, 2006 12:05 pm

lost attachment

Thu Feb 23, 2006 3:18 pm

Hi,

if somebody has this file,
please renew the attachment.


edge_level_triggering.pdf
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stephan_cadene
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Thu Feb 23, 2006 3:38 pm

Hi Romanua,

That's right.

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