AT91SAM7SE256B (Rev B of AT91SAM7SE256)

Discussion about SAM7 Series and ARM7TDMI based products.

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gusgus
Posts: 5
Joined: Tue Jan 15, 2013 10:44 am

AT91SAM7SE256B (Rev B of AT91SAM7SE256)

Thu Jun 05, 2014 10:02 am

We have product that work for years with AT91SAM7SE256. As this chip version is no longer available, we should switch to AT91SAM7SE256B. However, we discover an issue. The product is no longer able to understand an incoming frame in ISO7816 T=1 protocol (internal USART used). It understand the ATR, but after transmission, the reception is not effective. The device (smartcard) connected to our product, understands the frame because it responds, checked by oscilloscope. Checking the errata differences between the 2 chips, in the datasheet, give me no information on this behavior. Any idea? Regards,
gerhardf
Posts: 552
Joined: Thu Dec 02, 2004 2:28 pm

Re: AT91SAM7SE256B (Rev B of AT91SAM7SE256)

Fri Jun 06, 2014 9:27 pm

hello,
did you take care of the fact that rev. B has higher flahs accerss times than rev A?
Maybe this is the reason for your problems with rev. B. take a look at the datasheet at chapter "43.3.2.1EFC : Embedded Flash Access Time".
if this isn't the reason for your problem i would strongly recommend the atmel support.

regards gerhard
gusgus
Posts: 5
Joined: Tue Jan 15, 2013 10:44 am

Re: AT91SAM7SE256B (Rev B of AT91SAM7SE256)

Tue Jun 10, 2014 10:18 am

Thank for the answer.

Yes, the flash wait state is already stated to 2 for 48 MHz.

The issue previously described is the only one of all the others functionalities of the products.
mach
Posts: 4
Joined: Fri Jul 31, 2015 2:15 pm

Re: AT91SAM7SE256B (Rev B of AT91SAM7SE256)

Mon Aug 31, 2015 2:10 pm

Hello,

we have the same problem after an upgrade from AT91SAM7X256B to AT91SAM7X256C. We found that it helps to reset TX each time a transfer completes (TXEMPTY). What was your solution to the problem?

Regards,

Martin

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