Activation all Uart and Usart ports on SAMA5D27

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Joined: Fri Mar 02, 2018 4:40 pm

Activation all Uart and Usart ports on SAMA5D27

Fri Mar 02, 2018 5:01 pm

Hello,

I’m working on a SoM SAMA5D2 (Acmesystem Roadrunner)

I try to activate all Uart and Usart ports.
When I boot the board I see that some of them are not usable.
I tried also to activate them one by one and in this case ports are ok, when they are enabled one by one all of them works correctly individually.
but for example if the uart1 the uart3 is activated in same time the uart3 is not available anymore.

Linux kernel version is 4.9.40 and AT91bootstrap 3.8.8.

Somebody have any experience to activating all serial ports on SAMA5D27 ?

.dts file is below.

Thnx !




/dts-v1/;

/ {
#address-cells = <0x1>;
#size-cells = <0x1>;
model = "Acme Systems RoadRunner";
compatible = "atmel,sama5d2-bertad2", "atmel,sama5d2", "atmel,sama5";
interrupt-parent = <0x1>;

chosen {
stdout-path = "serial0:115200n8";
bootargs = "mem=256M console=ttyS1,115200 root=/dev/mmcblk0p2 rootfstype=ext4 rw rootwait consoleblank=0";
};

aliases {
serial0 = "/ahb/apb/serial@f8020000";
serial1 = "/ahb/apb/serial@fc008000";
tcb0 = "/ahb/apb/timer@f800c000";
tcb1 = "/ahb/apb/timer@f8010000";
};

memory {
device_type = "memory";
reg = <0x20000000 0x80000>;
};

cpus {
#address-cells = <0x1>;
#size-cells = <0x0>;

cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a5";
reg = <0x0>;
next-level-cache = <0x2>;
};
};

pmu {
compatible = "arm,cortex-a5-pmu";
interrupts = <0x2 0x4 0x0>;
};

etb {
compatible = "arm,coresight-etb10", "arm,primecell";
reg = <0x740000 0x1000>;
clocks = <0x3>;
clock-names = "apb_pclk";

port {

endpoint {
slave-mode;
remote-endpoint = <0x4>;
linux,phandle = <0x5>;
phandle = <0x5>;
};
};
};

etm {
compatible = "arm,coresight-etm3x", "arm,primecell";
reg = <0x73c000 0x1000>;
clocks = <0x3>;
clock-names = "apb_pclk";

port {

endpoint {
remote-endpoint = <0x5>;
linux,phandle = <0x4>;
phandle = <0x4>;
};
};
};

clocks {

slow_xtal {
compatible = "fixed-clock";
#clock-cells = <0x0>;
clock-frequency = <0x8000>;
linux,phandle = <0x3a>;
phandle = <0x3a>;
};

main_xtal {
compatible = "fixed-clock";
#clock-cells = <0x0>;
clock-frequency = <0xb71b00>;
linux,phandle = <0x1a>;
phandle = <0x1a>;
};
};

sram@00200000 {
compatible = "mmio-sram";
reg = <0x200000 0x20000>;
};

ahb {
compatible = "simple-bus";
#address-cells = <0x1>;
#size-cells = <0x1>;
ranges;

gadget@00300000 {
#address-cells = <0x1>;
#size-cells = <0x0>;
compatible = "atmel,sama5d3-udc";
reg = <0x300000 0x100000 0xfc02c000 0x400>;
interrupts = <0x2a 0x4 0x2>;
clocks = <0x6 0x7>;
clock-names = "pclk", "hclk";
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <0x8>;

ep@0 {
reg = <0x0>;
atmel,fifo-size = <0x40>;
atmel,nb-banks = <0x1>;
};

ep@1 {
reg = <0x1>;
atmel,fifo-size = <0x400>;
atmel,nb-banks = <0x3>;
atmel,can-dma;
atmel,can-isoc;
};

ep@2 {
reg = <0x2>;
atmel,fifo-size = <0x400>;
atmel,nb-banks = <0x3>;
atmel,can-dma;
atmel,can-isoc;
};

ep@3 {
reg = <0x3>;
atmel,fifo-size = <0x400>;
atmel,nb-banks = <0x2>;
atmel,can-dma;
atmel,can-isoc;
};

ep@4 {
reg = <0x4>;
atmel,fifo-size = <0x400>;
atmel,nb-banks = <0x2>;
atmel,can-dma;
atmel,can-isoc;
};

ep@5 {
reg = <0x5>;
atmel,fifo-size = <0x400>;
atmel,nb-banks = <0x2>;
atmel,can-dma;
atmel,can-isoc;
};

ep@6 {
reg = <0x6>;
atmel,fifo-size = <0x400>;
atmel,nb-banks = <0x2>;
atmel,can-dma;
atmel,can-isoc;
};

ep@7 {
reg = <0x7>;
atmel,fifo-size = <0x400>;
atmel,nb-banks = <0x2>;
atmel,can-dma;
atmel,can-isoc;
};

ep@8 {
reg = <0x8>;
atmel,fifo-size = <0x400>;
atmel,nb-banks = <0x2>;
atmel,can-isoc;
};

ep@9 {
reg = <0x9>;
atmel,fifo-size = <0x400>;
atmel,nb-banks = <0x2>;
atmel,can-isoc;
};

ep@10 {
reg = <0xa>;
atmel,fifo-size = <0x400>;
atmel,nb-banks = <0x2>;
atmel,can-isoc;
};

ep@11 {
reg = <0xb>;
atmel,fifo-size = <0x400>;
atmel,nb-banks = <0x2>;
atmel,can-isoc;
};

ep@12 {
reg = <0xc>;
atmel,fifo-size = <0x400>;
atmel,nb-banks = <0x2>;
atmel,can-isoc;
};

ep@13 {
reg = <0xd>;
atmel,fifo-size = <0x400>;
atmel,nb-banks = <0x2>;
atmel,can-isoc;
};

ep@14 {
reg = <0xe>;
atmel,fifo-size = <0x400>;
atmel,nb-banks = <0x2>;
atmel,can-isoc;
};

ep@15 {
reg = <0xf>;
atmel,fifo-size = <0x400>;
atmel,nb-banks = <0x2>;
atmel,can-isoc;
};
};

ohci@00400000 {
compatible = "atmel,at91rm9200-ohci", "usb-ohci";
reg = <0x400000 0x100000>;
interrupts = <0x29 0x4 0x2>;
clocks = <0x9 0x9 0xa>;
clock-names = "ohci_clk", "hclk", "uhpck";
status = "okay";
num-ports = <0x3>;
pinctrl-names = "default";
pinctrl-0 = <0xb>;
};

ehci@00500000 {
compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
reg = <0x500000 0x100000>;
interrupts = <0x29 0x4 0x2>;
clocks = <0x7 0x9>;
clock-names = "usb_clk", "ehci_clk";
status = "okay";
};

cache-controller@00a00000 {
compatible = "arm,pl310-cache";
reg = <0xa00000 0x1000>;
interrupts = <0x3f 0x4 0x4>;
cache-unified;
cache-level = <0x2>;
linux,phandle = <0x2>;
phandle = <0x2>;
};

nand@80000000 {
compatible = "atmel,sama5d2-nand";
#address-cells = <0x1>;
#size-cells = <0x1>;
ranges;
reg = <0x80000000 0x8000000 0xf8014070 0x490 0xf8014500 0x200 0x40000 0x18000>;
interrupts = <0x11 0x4 0x6>;
atmel,nand-addr-offset = <0x15>;
atmel,nand-cmd-offset = <0x16>;
atmel,nand-has-dma;
atmel,has-pmecc;
atmel,pmecc-lookup-table-offset = <0x0 0x8000>;
status = "disabled";

nfc@c0000000 {
compatible = "atmel,sama5d3-nfc";
#address-cells = <0x1>;
#size-cells = <0x1>;
reg = <0xc0000000 0x8000000 0xf8014000 0x70 0x100000 0x100000>;
clocks = <0xc>;
atmel,write-by-sram;
};
};

sdio-host@a0000000 {
compatible = "atmel,sama5d2-sdhci";
reg = <0xa0000000 0x300>;
interrupts = <0x1f 0x4 0x0>;
clocks = <0xd 0xe 0xf>;
clock-names = "hclock", "multclk", "baseclk";
status = "disabled";
};

sdio-host@b0000000 {
compatible = "atmel,sama5d2-sdhci";
reg = <0xb0000000 0x300>;
interrupts = <0x20 0x4 0x0>;
clocks = <0x10 0x11 0xf>;
clock-names = "hclock", "multclk", "baseclk";
status = "okay";
bus-width = <0x4>;
pinctrl-names = "default";
pinctrl-0 = <0x12>;
non-removable;
};

apb {
compatible = "simple-bus";
#address-cells = <0x1>;
#size-cells = <0x1>;
ranges;

hlcdc@f0000000 {
compatible = "atmel,sama5d2-hlcdc";
reg = <0xf0000000 0x2000>;
interrupts = <0x2d 0x4 0x0>;
clocks = <0x13 0x14 0x15>;
clock-names = "periph_clk", "sys_clk", "slow_clk";
status = "disabled";

hlcdc-display-controller {
compatible = "atmel,hlcdc-display-controller";
#address-cells = <0x1>;
#size-cells = <0x0>;

port@0 {
#address-cells = <0x1>;
#size-cells = <0x0>;
reg = <0x0>;
};
};

hlcdc-pwm {
compatible = "atmel,hlcdc-pwm";
#pwm-cells = <0x3>;
};
};

ramc@f000c000 {
compatible = "atmel,sama5d3-ddramc";
reg = <0xf000c000 0x200>;
clocks = <0x16 0x17>;
clock-names = "ddrck", "mpddr";
};

dma-controller@f0010000 {
compatible = "atmel,sama5d4-dma";
reg = <0xf0010000 0x1000>;
interrupts = <0x6 0x4 0x0>;
#dma-cells = <0x1>;
clocks = <0x18>;
clock-names = "dma_clk";
linux,phandle = <0x24>;
phandle = <0x24>;
};

pmc@f0014000 {
compatible = "atmel,sama5d2-pmc", "syscon";
reg = <0xf0014000 0x160>;
interrupts = <0x4a 0x4 0x7>;
interrupt-controller;
#address-cells = <0x1>;
#size-cells = <0x0>;
#interrupt-cells = <0x1>;
linux,phandle = <0x19>;
phandle = <0x19>;

main_rc_osc {
compatible = "atmel,at91sam9x5-clk-main-rc-osc";
#clock-cells = <0x0>;
interrupt-parent = <0x19>;
interrupts = <0x11>;
clock-frequency = <0xb71b00>;
clock-accuracy = <0x5f5e100>;
linux,phandle = <0x1b>;
phandle = <0x1b>;
};

main_osc {
compatible = "atmel,at91rm9200-clk-main-osc";
#clock-cells = <0x0>;
interrupt-parent = <0x19>;
interrupts = <0x0>;
clocks = <0x1a>;
linux,phandle = <0x1c>;
phandle = <0x1c>;
};

mainck {
compatible = "atmel,at91sam9x5-clk-main";
#clock-cells = <0x0>;
interrupt-parent = <0x19>;
interrupts = <0x10>;
clocks = <0x1b 0x1c>;
linux,phandle = <0xf>;
phandle = <0xf>;
};

pllack {
compatible = "atmel,sama5d3-clk-pll";
#clock-cells = <0x0>;
interrupt-parent = <0x19>;
interrupts = <0x1>;
clocks = <0xf>;
reg = <0x0>;
atmel,clk-input-range = <0xb71b00 0xb71b00>;
#atmel,pll-clk-output-range-cells = <0x4>;
atmel,pll-clk-output-ranges = <0x23c34600 0x47868c00 0x0 0x0>;
linux,phandle = <0x1d>;
phandle = <0x1d>;
};

plladivck {
compatible = "atmel,at91sam9x5-clk-plldiv";
#clock-cells = <0x0>;
clocks = <0x1d>;
linux,phandle = <0x1e>;
phandle = <0x1e>;
};

utmick {
compatible = "atmel,at91sam9x5-clk-utmi";
#clock-cells = <0x0>;
interrupt-parent = <0x19>;
interrupts = <0x6>;
clocks = <0xf>;
linux,phandle = <0x7>;
phandle = <0x7>;
};

masterck {
compatible = "atmel,at91sam9x5-clk-master";
#clock-cells = <0x0>;
interrupt-parent = <0x19>;
interrupts = <0x3>;
clocks = <0x15 0xf 0x1e 0x7>;
atmel,clk-output-range = <0x7641700 0x9e4f580>;
atmel,clk-divisors = <0x1 0x2 0x4 0x3>;
linux,phandle = <0x3>;
phandle = <0x3>;
};

h32mxck {
#clock-cells = <0x0>;
compatible = "atmel,sama5d4-clk-h32mx";
clocks = <0x3>;
linux,phandle = <0x23>;
phandle = <0x23>;
};

usbck {
compatible = "atmel,at91sam9x5-clk-usb";
#clock-cells = <0x0>;
clocks = <0x1e 0x7>;
linux,phandle = <0x1f>;
phandle = <0x1f>;
};

progck {
compatible = "atmel,at91sam9x5-clk-programmable";
#address-cells = <0x1>;
#size-cells = <0x0>;
interrupt-parent = <0x19>;
clocks = <0x15 0xf 0x1e 0x7 0x3>;

prog0 {
#clock-cells = <0x0>;
reg = <0x0>;
interrupts = <0x8>;
linux,phandle = <0x20>;
phandle = <0x20>;
};

prog1 {
#clock-cells = <0x0>;
reg = <0x1>;
interrupts = <0x9>;
linux,phandle = <0x21>;
phandle = <0x21>;
};

prog2 {
#clock-cells = <0x0>;
reg = <0x2>;
interrupts = <0xa>;
linux,phandle = <0x22>;
phandle = <0x22>;
};
};

systemck {
compatible = "atmel,at91rm9200-clk-system";
#address-cells = <0x1>;
#size-cells = <0x0>;

ddrck {
#clock-cells = <0x0>;
reg = <0x2>;
clocks = <0x3>;
linux,phandle = <0x16>;
phandle = <0x16>;
};

lcdck {
#clock-cells = <0x0>;
reg = <0x3>;
clocks = <0x3>;
linux,phandle = <0x14>;
phandle = <0x14>;
};

uhpck {
#clock-cells = <0x0>;
reg = <0x6>;
clocks = <0x1f>;
linux,phandle = <0xa>;
phandle = <0xa>;
};

udpck {
#clock-cells = <0x0>;
reg = <0x7>;
clocks = <0x1f>;
};

pck0 {
#clock-cells = <0x0>;
reg = <0x8>;
clocks = <0x20>;
};

pck1 {
#clock-cells = <0x0>;
reg = <0x9>;
clocks = <0x21>;
};

pck2 {
#clock-cells = <0x0>;
reg = <0xa>;
clocks = <0x22>;
};

iscck {
#clock-cells = <0x0>;
reg = <0x12>;
clocks = <0x3>;
};
};

periph32ck {
compatible = "atmel,at91sam9x5-clk-peripheral";
#address-cells = <0x1>;
#size-cells = <0x0>;
clocks = <0x23>;

macb0_clk {
#clock-cells = <0x0>;
reg = <0x5>;
atmel,clk-output-range = <0x0 0x4f27ac0>;
linux,phandle = <0x29>;
phandle = <0x29>;
};

tdes_clk {
#clock-cells = <0x0>;
reg = <0xb>;
atmel,clk-output-range = <0x0 0x4f27ac0>;
linux,phandle = <0x4a>;
phandle = <0x4a>;
};

matrix1_clk {
#clock-cells = <0x0>;
reg = <0xe>;
};

hsmc_clk {
#clock-cells = <0x0>;
reg = <0x11>;
linux,phandle = <0xc>;
phandle = <0xc>;
};

pioA_clk {
#clock-cells = <0x0>;
reg = <0x12>;
atmel,clk-output-range = <0x0 0x4f27ac0>;
linux,phandle = <0x49>;
phandle = <0x49>;
};

flx0_clk {
#clock-cells = <0x0>;
reg = <0x13>;
atmel,clk-output-range = <0x0 0x4f27ac0>;
linux,phandle = <0x37>;
phandle = <0x37>;
};

flx1_clk {
#clock-cells = <0x0>;
reg = <0x14>;
atmel,clk-output-range = <0x0 0x4f27ac0>;
linux,phandle = <0x39>;
phandle = <0x39>;
};

flx2_clk {
#clock-cells = <0x0>;
reg = <0x15>;
atmel,clk-output-range = <0x0 0x4f27ac0>;
linux,phandle = <0x41>;
phandle = <0x41>;
};

flx3_clk {
#clock-cells = <0x0>;
reg = <0x16>;
atmel,clk-output-range = <0x0 0x4f27ac0>;
linux,phandle = <0x42>;
phandle = <0x42>;
};

flx4_clk {
#clock-cells = <0x0>;
reg = <0x17>;
atmel,clk-output-range = <0x0 0x4f27ac0>;
linux,phandle = <0x43>;
phandle = <0x43>;
};

uart0_clk {
#clock-cells = <0x0>;
reg = <0x18>;
atmel,clk-output-range = <0x0 0x4f27ac0>;
linux,phandle = <0x31>;
phandle = <0x31>;
};

uart1_clk {
#clock-cells = <0x0>;
reg = <0x19>;
atmel,clk-output-range = <0x0 0x4f27ac0>;
linux,phandle = <0x32>;
phandle = <0x32>;
};

uart2_clk {
#clock-cells = <0x0>;
reg = <0x1a>;
atmel,clk-output-range = <0x0 0x4f27ac0>;
linux,phandle = <0x34>;
phandle = <0x34>;
};

uart3_clk {
#clock-cells = <0x0>;
reg = <0x1b>;
atmel,clk-output-range = <0x0 0x4f27ac0>;
linux,phandle = <0x3e>;
phandle = <0x3e>;
};

uart4_clk {
#clock-cells = <0x0>;
reg = <0x1c>;
atmel,clk-output-range = <0x0 0x4f27ac0>;
linux,phandle = <0x40>;
phandle = <0x40>;
};

twi0_clk {
reg = <0x1d>;
#clock-cells = <0x0>;
atmel,clk-output-range = <0x0 0x4f27ac0>;
linux,phandle = <0x35>;
phandle = <0x35>;
};

twi1_clk {
#clock-cells = <0x0>;
reg = <0x1e>;
atmel,clk-output-range = <0x0 0x4f27ac0>;
linux,phandle = <0x46>;
phandle = <0x46>;
};

spi0_clk {
#clock-cells = <0x0>;
reg = <0x21>;
atmel,clk-output-range = <0x0 0x4f27ac0>;
linux,phandle = <0x27>;
phandle = <0x27>;
};

spi1_clk {
#clock-cells = <0x0>;
reg = <0x22>;
atmel,clk-output-range = <0x0 0x4f27ac0>;
linux,phandle = <0x3d>;
phandle = <0x3d>;
};

tcb0_clk {
#clock-cells = <0x0>;
reg = <0x23>;
atmel,clk-output-range = <0x0 0x4f27ac0>;
linux,phandle = <0x2d>;
phandle = <0x2d>;
};

tcb1_clk {
#clock-cells = <0x0>;
reg = <0x24>;
atmel,clk-output-range = <0x0 0x4f27ac0>;
linux,phandle = <0x2e>;
phandle = <0x2e>;
};

pwm_clk {
#clock-cells = <0x0>;
reg = <0x26>;
atmel,clk-output-range = <0x0 0x4f27ac0>;
};

adc_clk {
#clock-cells = <0x0>;
reg = <0x28>;
atmel,clk-output-range = <0x0 0x4f27ac0>;
linux,phandle = <0x48>;
phandle = <0x48>;
};

uhphs_clk {
#clock-cells = <0x0>;
reg = <0x29>;
atmel,clk-output-range = <0x0 0x4f27ac0>;
linux,phandle = <0x9>;
phandle = <0x9>;
};

udphs_clk {
#clock-cells = <0x0>;
reg = <0x2a>;
atmel,clk-output-range = <0x0 0x4f27ac0>;
linux,phandle = <0x6>;
phandle = <0x6>;
};

ssc0_clk {
#clock-cells = <0x0>;
reg = <0x2b>;
atmel,clk-output-range = <0x0 0x4f27ac0>;
};

ssc1_clk {
#clock-cells = <0x0>;
reg = <0x2c>;
atmel,clk-output-range = <0x0 0x4f27ac0>;
};

trng_clk {
#clock-cells = <0x0>;
reg = <0x2f>;
atmel,clk-output-range = <0x0 0x4f27ac0>;
linux,phandle = <0x45>;
phandle = <0x45>;
};

pdmic_clk {
#clock-cells = <0x0>;
reg = <0x30>;
atmel,clk-output-range = <0x0 0x4f27ac0>;
linux,phandle = <0x2f>;
phandle = <0x2f>;
};

i2s0_clk {
#clock-cells = <0x0>;
reg = <0x36>;
atmel,clk-output-range = <0x0 0x4f27ac0>;
};

i2s1_clk {
#clock-cells = <0x0>;
reg = <0x37>;
atmel,clk-output-range = <0x0 0x4f27ac0>;
};

classd_clk {
#clock-cells = <0x0>;
reg = <0x3b>;
atmel,clk-output-range = <0x0 0x4f27ac0>;
};
};

periph64ck {
compatible = "atmel,at91sam9x5-clk-peripheral";
#address-cells = <0x1>;
#size-cells = <0x0>;
clocks = <0x3>;

dma0_clk {
#clock-cells = <0x0>;
reg = <0x6>;
linux,phandle = <0x18>;
phandle = <0x18>;
};

dma1_clk {
#clock-cells = <0x0>;
reg = <0x7>;
};

aes_clk {
#clock-cells = <0x0>;
reg = <0x9>;
linux,phandle = <0x26>;
phandle = <0x26>;
};

aesb_clk {
#clock-cells = <0x0>;
reg = <0xa>;
};

sha_clk {
#clock-cells = <0x0>;
reg = <0xc>;
linux,phandle = <0x25>;
phandle = <0x25>;
};

mpddr_clk {
#clock-cells = <0x0>;
reg = <0xd>;
linux,phandle = <0x17>;
phandle = <0x17>;
};

matrix0_clk {
#clock-cells = <0x0>;
reg = <0xf>;
};

sdmmc0_hclk {
#clock-cells = <0x0>;
reg = <0x1f>;
linux,phandle = <0xd>;
phandle = <0xd>;
};

sdmmc1_hclk {
#clock-cells = <0x0>;
reg = <0x20>;
linux,phandle = <0x10>;
phandle = <0x10>;
};

lcdc_clk {
#clock-cells = <0x0>;
reg = <0x2d>;
linux,phandle = <0x13>;
phandle = <0x13>;
};
blue_z
Location: USA
Posts: 1690
Joined: Thu Apr 19, 2007 10:15 pm

Re: Activation all Uart and Usart ports on SAMA5D27

Tue Mar 06, 2018 2:36 am

dcresearch wrote:Somebody have any experience to activating all serial ports on SAMA5D27 ?
Is this an all or nothing proposition?

You seem to have reduced the problem to a simple case (e.g. UART1 and UART3), so how long are you going to wait for a response before you investigate deeper than determining a port "is not available anymore" (whatever that means)?

dcresearch wrote: .dts file is below.
For what configuration?
What you have posted is almost unreadable; learn to use the code block to preserve indentation.
It's not a valid Device Tree file; the braces are obviously mismatched.
Is this the output from the preprocessor? Why?
A search of this "dts" finds no nodes for any U[S]ARTs.

Regards

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